Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2002-04-01

2002-12-10

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000

Reexamination Certificate

active

06493256

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a memory cell structure of a CMOS static RAM.
2. Description of the Background Art
FIG. 15
is a circuit diagram showing an exemplary memory cell (memory circuit) of multiport memory in the background art, e.g., disclosed in Japanese Patent Publication No. 58-27917 (FIG.
4
).
As shown in
FIG. 15
, PMOS transistors PI
1
and PI
2
and NMOS transistors NI
1
and NI
2
constitute a memory cell storage unit
9
. Sources of the PMOS transistors PI
1
and PI
2
are connected to a power supply VDD, and sources of the NMOS transistors NI
1
and NI
2
are connected to a ground potential GND. Drains of the PMOS transistor PI
1
and the NMOS transistor NIl and gates of the PMOS transistor PI
2
and the NMOS transistor NI
2
are commonly connected to a memory terminal
21
, and drains of the PMOS transistor PI
2
and the NMOS transistor NI
2
and gates of the PMOS transistor PI
1
and the NMOS transistor NI
1
are commonly connected to a memory terminal
22
.
Specifically, a first CMOS inverter consisting of the PMOS transistor PI
1
and the NMOS transistor NI
1
and a second CMOS inverter consisting of the PMOS transistor PI
2
and the NMOS transistor NI
2
are cross-connected, to form the memory cell storage unit
9
.
A drain of an access (NMOS) transistor NA
1
is connected to the memory terminal
21
. A bit line BL
1
is connected to a source of an access transistor N
1
and a word line WL
1
is connected to a gate thereof. A drain of an access (NMOS) transistor NA
2
is connected to the memory terminal
22
. A bit line BL
2
is connected to a source of an access transistor N
2
and a word line WL
2
is connected to a gate thereof.
Further, gates of NMOS transistors N
21
and N
22
are connected to the memory terminals
21
and
22
, respectively, and sources thereof are commonly connected the ground potential GND. Sources of NMOS transistors N
23
and N
24
are connected to drains of the NMOS transistors N
21
and N
22
, respectively. A read word line RWL
1
and a read bit line RBL
1
are connected to a gate and a drain of the NMOS transistor N
23
, respectively, and a read word line RWL
2
and a read bit line RBL
2
are connected to a gate and a drain of the NMOS transistor N
24
, respectively.
With respect to this structure, an operation of the memory cell storage unit
9
of multiport memory in the background art shown in
FIG. 15
will be discussed. The memory terminals
21
and
22
have a complementary relation, and for example, when the memory terminal
21
is in a logical “H” state, the memory terminal
22
comes into a logical “L” state, being stable. Conversely, when the memory terminal
21
is in the logical “L” state, the memory terminal
22
comes into the logical “H” state, being stable. Thus, this structure can hold stored data of the two stable states, depending on whether the states of the memory terminals
21
and
22
are “H” or “L”.
If the memory terminal
21
is stable in the logical “H” state (in other words, the memory terminal
22
is in the logical “L” state), the PMOS transistor pI
1
is in an ON state and the PMOS transistor PI
2
is in an OFF state. Further, the NMOS transistor NI
1
is in the OFF state and the NMOS transistor NI
2
is in the ON state.
Next, a read/write operation using the word line WL
1
(WL
2
) and the bit line BL
1
(BL
2
) will be discussed. When the word line WL
1
is in the “L” state, the transistor NA
1
is in the OFF state, and the memory terminal
21
is electrically cut off with the bit line BL
1
which corresponds to a read/write terminal for data. In other words, the stored data is held. When the word line WL
1
is brought into the “H” state from the “L” state in response to an external signal, the transistor NA
1
comes into the ON state from the OFF state and the memory terminal
21
electrically gets connected to the bit line BL
1
.
In this case, if the bit line BL
1
is not externally driven, the data of the memory terminal
21
is propagated to the bit line BL
1
through the transistor NA
1
and read out. Thus performed is a read operation in the read/write operation.
On the other hand, when the word line WL
1
is in the “H” state, if the bit line BL
1
is strongly driven into the “L” or “H” state by a not-shown external circuit, the data of the bit line BL
1
which is driven is propagated to the memory terminal
21
through the transistor NA
1
and data of the memory terminal
21
is rewritten by the data of the bit line BL
1
. Thus performed is a write operation in the read/write operation.
When the word line WL
1
is returned to the “L” state from the “H” state by an external signal, the memory terminal
21
comes into a hold-mode again. An operation of a port on the side of the transistor NA
2
connected to the memory terminal
22
is the same as the above operation and therefore not discussed herein.
Next, a read operation using the read word line RWL
1
(RWL
2
) and the read bit line RBL
1
(RBL
2
) will be discussed. When the read word line RWL
1
is in the “L” state, the NMOS transistor N
23
is in the OFF state, and a read terminal m
1
is electrically cut off with the read bit line RBL
1
. In an initial state, the read bit line RBL
1
is precharged in the “H” state by a not-shown precharge circuit.
When the read word line RWL
1
is brought into the “H” state from the “L” state in response to an external signal, the NMOS transistor N
23
comes into the ON state from the OFF state and the memory terminal m
1
electrically gets connected to the read bit line RBL
1
. If the hold-mode of the memory terminal
21
is “H”, the NMOS transistor N
21
is in the ON state and the read bit line RBL
1
electrically gets connected to the ground potential GND through the NMOS transistors N
23
and N
21
. Therefore, the read bit line RBL
1
is brought into the “L” state from the “H” state and data of “L” which is inverted data of the memory terminal
21
is read out.
Conversely, if the hold-mode of the memory terminal
21
is “L”, the NMOS transistor N
21
is in the OFF state and the read bit line RBL
1
is electrically cut off with the ground potential GND. Therefore, the read bit line RBL
1
remains the “H” state and data of “H” which is inverted data of the memory terminal
21
is read out. When the read word line RWL
1
is returned to the “L” state from the “H” state by an external signal, the memory terminal m
1
gets cut off with the read bit line RBL
1
again and the read bit line RBL
1
is precharged into the “H” state again for the next read operation. Further, the read bit line RBL
1
and the memory terminal
21
are not electrically connected to each other and no write operation is performed by the NMOS transistor N
23
. A read operation of a port on the side of the NMOS transistor N
24
connected to another memory terminal m
2
is the same as the above operation and therefore not discussed.
As discussed above, the memory cell including the memory cell storage unit
9
of multiport memory in the background art shown in
FIG. 15
has a structure comprising two ports for reading and writing and two ports for only reading.
FIG. 15
shows a four-port memory cell consisting of totally ten MOS transistors, i.e., eight NMOS transistors and two PMOS transistors.
The four-port memory cell is constituted of ten transistors as shown in
FIG. 15
, and in the structure of a multiport memory cell, like this example, the number of transistors constituting the multiport memory cell increases depending on the number of ports and this disadvantageously results in enlargement of cell area.
SUMMARY OF THE INVENTION
The present invention is directed to a semiconductor memory device. According to a first aspect of the present invention, the semiconductor memory device has a memory cell storage unit for data storage formed in a semiconductor substrate. The memory cell storage unit of the first aspect comprises first and second MIS transistors both of a first conductivity type, one electrode of the

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