Method to reduce capacitance for copper interconnect structures

Details Method to reduce capacitance for copper interconnect structures Method to reduce capacitance for copper interconnect structures

1999-08-18

2002-12-17

Sherry, Michael (Department: 2829)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S687000

Reexamination Certificate

active

06495452

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to reduce the capacitance of semiconductor devices, comprised with copper interconnect structures.
(2) Description of Prior Art
The use of copper interconnect structures, has resulted in an increase in semiconductor device performance, when compared to counterparts fabricated using less conductive aluminum based, interconnect structures. However the use of dielectric barrier layers, such as a high dielectric constant silicon nitride layer, needed to prevent diffusion of copper, into, or poisoning of, overlying insulator layers, such as silicon oxide, have negated part of the performance increases resulting from the use of conductive copper structures. A blanket layer, of a high dielectric constant barrier layer, such as silicon nitride, is deposited after definition of the copper structure, and only removed from the region of the copper structure, to be used for contact by an overlying conductive structure. The remaining regions of the high dielectric constant silicon nitride layer, result in unwanted capacitances and decreased device performance.
This invention will describe a procedure in which a tantalum, or tantalum nitride, barrier layer, is used to prevent the interaction between the underlying copper interconnect structure, and an overlying insulator layer. However this invention will teach a process in which the barrier layer is patterned to remain only overlying the top surface of the underlying copper structure, removed from all other regions of the semiconductor device. The use of this novel procedure, using a photoresist shape as an etch mask for definition of the barrier layer shape, and where the photoresist shape is formed via exposure of a negative photoresist layer, using the same photomask that was previously used to create the damascene opening, in which the copper structure resides, allows creation of the barrier shape, overlying only the top surface of the copper structure, thus eliminating the need for a silicon nitride barrier layer, and thus resulting in reductions in capacitance, and increases in device performance. Prior art, such as Schacham-Diamand et al, in U.S. Pat. No. 5,824,599, and Bai et al, in U.S. Pat. No. 5,714,418, describe the use of silicon nitride barrier layers, for copper structures, while Chan et al, in U.S. Pat. No. 5.744,376, describes the use of either silicon nitride, aluminum oxide, or tantalum oxide barriers, for copper structures. However none of these prior arts describe the use of a conductive barrier layer, such as tantalum or tantalum nitride, defined overlying only the top surface of the underlying copper structure.
SUMMARY OF THE INVENTION
It is an object of this invention to fabricate a barrier layer, to prevent diffusion, or poisoning, from a underlying copper structure, to an overlying insulator layer.
It is another object of this invention to define a barrier layer shape, only on the top surface of the underlying copper structure.
It is still another object of this invention to create a tantalum or tantalum nitride barrier layer shape, only on the top surface of the underlying copper structure, via use of a reactive ion etching procedure, featuring the use a photoresist shape as an etch mask, where the photoresist shape is created using a negative photoresist material, and exposure using the same photomask that was previously used to define the opening, in an insulator layer, used for the damascene copper structure.
In accordance with the present invention a method is described for fabricating a damascene copper structure, featuring a conductive barrier layer, located only on the top surface of the damascene copper structure. An opening is made in a first insulator layer, using a first photomask, and a positive photoresist layer, exposing either a portion of the top surface of an underlying, lower interconnect structure, or a portion of the top surface of an active device region, in a semiconductor substrate, located at the bottom of the opening. After deposition of a first barrier layer, and of a copper layer, completely filling the opening in the first insulator layer, a chemical mechanical polishing, (CMP), procedure, is used to remove the regions of copper, and the regions of the first barrier layer, residing on the top surface of the first insulator layer, creating a damascene copper structure, in the opening in the first insulator layer. A second barrier layer, comprised of either tantalum or tantalum nitride is deposited, then defined overlying only the top surface of copper structure, via use of a reactive ion etching procedure, using a photoresist shape as a mask, where the photoresist mask was formed via exposure of a negative photoresist layer, using the first photomask. A second insulator layer is deposited, followed by the formation of a damascene, or dual damascene opening, in the second insulator layer, exposing a portion of the top surface of the second barrier layer, overlying the damascene copper structure. An upper metal interconnect structure is then formed in the opening in the second insulator layer, overlying, and contacting, a portion of the top surface of the second barrier layer.


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