Semiconductor device manufacturing: process – Chemical etching – Having liquid and vapor etching steps
Reexamination Certificate
1999-10-29
2002-11-26
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Chemical etching
Having liquid and vapor etching steps
C438S233000, C438S400000, C438S739000, C438S755000
Reexamination Certificate
active
06486067
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to processes used to fabricate semiconductor devices, and more specifically to a process used to fabricate a self-aligned contact structure, where one of the components of the self-aligned contact structure is a metal silicide layer.
(2) Description of the Prior art
In semiconductor integrated circuit manufacturing, metals are formed into patterned layers to make electrical connections to and between individual devices on a silicon substrate, such as sources, drains, and gates of field effect transistors (FET's). Metal layers, dielectric layers, and other structures, such as gate structures may be deposited over the substrate. In the simplest method, a surface is blanketed with metal and the deposited metal is then patterned to form the desired interconnection configuration. In the current semiconductor processes, aluminum is the most widely used material, but other refractory materials are being used, tungsten in particular. Blanket layers of metal can be deposited by low pressure chemical vapor deposition (LPCVD) and the patterning of metal layers can be accomplished by conventional lithographic and etching techniques.
To form more accurate contacts between buried devices in the substrate, such as source and drain impurity regions, a method of forming self aligned contacts (SAC) is often used. A self aligned contact is formed by patterning layers of structures around a contact area so that when a metal layer is formed over the structures and the contact region, the metal forms an electrical connection with the impurity regions in the substrate, e.g. a source or drain region. However, self aligned contacts often suffer from several problems., such as poor metal contact with the substrate and also because of poor electrical isolation between the contact and the gate electrode.
A conventional process for forming a self aligned contact with a metal layer is shown in
FIGS. 1 through 4
. As shown in
FIG. 1
, gate structures
28
, and
30
are formed on a semiconductor substrate
10
using conventional processes which are commonly known to those skilled in the art. Therefore only the elements will be described, not the processes. The gate structures
28
,
30
are comprised of gate oxide layer
16
, gate
18
, top oxide layer
19
(also referred to as self aligned contact oxide layer), and oxide sidewall spacers
24
. The substrate
10
has two silicon substrate diffusions, a N− diffusion (referred to as a lightly doped source or drain)
12
and a N+ diffusion (referred to as a heavily doped source or drain)
14
.
Referring to
FIG. 2
, an inter-poly oxide layer
32
is formed on the device surface. The term “device surface” is used herein to include all layers and structures formed on the substrate. Next, portions of the inter-poly oxide
32
between the gate structures
28
,
30
are etched (called a self-aligned contact etch) to expose the oxide sidewalls
24
and the contact area
26
, as illustrated in FIG.
3
.
Subsequently, a polysilicon layer
34
is formed with a thickness in the range of 500 to 600 angstroms on the device surface, as illustrated in FIG.
4
. The polysilicon layer
34
is then implanted with impurity ions to increase its conductivity. Polysilicon layer
34
is deposited between the metal layer
36
and the oxide layers
24
,
32
to prevent the pealing of the metal layer
34
from the device surface. A metal layer
36
, preferably tungsten silicide, is formed over the polysilicon layer
34
. The tungsten silicide layer
36
forms an electrical connection with the substrate and the underlying source/drain region
12
,
14
in the contact area
26
. This process is self aligning since the tungsten silicide connections contacts
26
to the source/drain diffusion
12
,
14
are defined using the oxide sidewall spacers
24
as the mask. This self aligning contact process eliminates less precise and more costly lithography process steps.
There are numerous patents that describe self aligned contact structure and suggest various improvements thereto. U.S. Pat. Nos. 5,480,814 and 5,795,827 describe processes for reducing the contact resistance to the source/drain regions. U.S. Pat. No. 5,923,988 describes and claims a process for forming an improved self aligned contact which employs various reactants for forming tungsten silicide layers combined with a dual anneal to improve the contact. U.S. Pat. No. 5,899,722 describes a process for forming a SAC which used a dual spacer structure.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an method to for forming a self aligned contact with an improved electrical isolation between the self aligned contact and the gate electrode.
Another object of the invention is to provide a more electrically stable SAC contact.
An object of the invention is to provide an improved integrated circuit device which includes a self aligned contact between two gate structures on a semiconductor
In accordance with the above objectives, there is provided an improved method of fabricating a polycide self aligned contact structure for MOSFET devices on a semiconductor substrate in which the electrical isolation between the contact and the gate structure is greatly improved. In the process a first polysilicon layer is formed on the substrate, followed by a first metal silicide layer, and a first insulator layer. The top first insulator layer is patterned anisotropically to form openings that define gate structures. The exposed metal silicide layer is dip etched in an etchant for metal silicide to form an undercut beneath the overlying peripheral edge of the first insulator layer. The anisotropic patterning is continued through metal silicide layer and the underlying first polysilicon layer. A first conductivity imparting dopant is implanted to form lightly doped source and drain regions. A second insulator layer is deposited on the surface and into the openings, including into the undercuts formed during the dip etch. The second insulator layer is anisotropically etched to form sidewall spacers in the openings. A second implant is made forming heavily doped source and drain regions. The conventional metal silicide contacts, and an interconnect metallization structure are thereafter formed.
REFERENCES:
patent: 5480814 (1996-01-01), Wuu et al.
patent: 5545578 (1996-08-01), Park et al.
patent: 5776822 (1998-07-01), Fujii et al.
patent: 5795827 (1998-08-01), Liaw et al.
patent: 5899722 (1999-05-01), Huang
patent: 5923988 (1999-07-01), Cheng et al.
patent: 5989987 (1999-11-01), Kuo
patent: 2-54960 (1990-02-01), None
patent: 3-209775 (1991-09-01), None
Liu Hsueh-Heng
Shen Yun-Hung
Ackerman Stephen B.
Brophy Jamie L.
Jr. Carl Whitehead
Saile George O.
Stoffel Wolmar J
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