Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-02-22
2002-11-19
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S110000, C438S113000, C438S613000
Reexamination Certificate
active
06482730
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to a method for manufacturing a semiconductor device. In particular, it pertains to a method for manufacturing a semiconductor device that can package semiconductor chips in a wafer state.
BACKGROUND OF THE INVENTION
In the manufacturing field of semiconductor devices, there is an ongoing effort to further miniaturize a single packaged semiconductor device. The initial effort to miniaturize semiconductor devices involved the reduction of the dimensions of the semiconductor chips themselves. With the reduction of semiconductor chips, the number of chips, which can be obtained from one wafer is increased, and the manufacturing cost is reduced. At the same time,, since the distance required by the electrons to move between the respective elements can be shortened, the operating speed of the device can be increased. With the development of fine machining technologies, the chip size of semiconductor devices with equivalent functions can be decreased even more. Currently, the most advanced design unit is around 0.25 &mgr;m, and according to the rule, 20 million or more transistors can be formed on one semiconductor chip.
The next effort in miniaturizing semiconductor devices is to produce packages for sealing the semiconductor chips of sizes that are as close as possible to the sizes of the semiconductor chips being housed. One actual result of this effort is a semiconductor device called a chip size package (CSP) or a chip scale package. In a chip size package, terminals (hereinafter called external terminals) that connect to a substrate (hereinafter called external substrate), on which a semiconductor device is mounted, are two-dimensionally arranged over the surface of the semiconductor chips so that the chip can be made formed with approximately the same size as the package. In the above-mentioned description, the package size is decreased to make it approximately the same as the semiconductor chip size, so that the mounting area is decreased and the wiring length of chip electrodes and external terminals is shortened. Thereby, similar to the case where the above-mentioned semiconductor chips themselves are reduced, the operating speed of the semiconductor device is improved.
On the other hand, even though the package size is decreased, the manufacturing costs are not considerably lowered. The reason for this is that the package must be processed for each semiconductor chip cut out of the wafer so the number of processes is constant, and even though the package size is decreased, there is no change in productivity.
Under this background, a technology for packaging semiconductor chips in a wafer state (hereinafter called wafer-level CSP) has been proposed, and its practical application has been developed by various companies. Wafer-level CSP is a semiconductor manufacturing technology that packages before each semiconductor chip is cut out of a wafer. In wafer-level CSP, since the package process can be integrated with the wafer process, the packaging costs and the manufacturing costs of the chips can be significantly lowered. For further details of wafer-level CSP, see “Nikkei Microdevice,” published by Nikkei BP Co., August 1998, pp. 44-71.
Wafer-level CSP patterns from structures in which the surface of a wafer is covered with a resin similar to the conventional chip size package. However, in this type of semiconductor device, the resin does not cover the sides of the semiconductor chips so the sealing reliability is lower relative to a conventional package. In addition, due to the difference in linear expansion coefficients between the wafer and resin, etc., the resin will often peel away from the interface with the wafer. Also, in such a semiconductor device, a high degree of flatness is required for the surface on the mounting side of the semiconductor chips, thus, the mounting surface requires a planarization process with a favorable yield that is suitable for the semiconductor device with the above-mentioned pattern.
SUMMARY OF THE INVENTION
The method for manufacturing the semiconductor device of the present invention includes the following processes. The method consists of a process that prepares a wafer on which there are several semiconductor elements with corresponding electrode pads exposed on the wafer surface; a process that forms wiring for electrically connecting the above-mentioned electrode pads and corresponding external terminals on the above-mentioned wafer; a process that forms conductive supports at each point of the above-mentioned wiring where the above-mentioned external terminals are arranged; a process that forms a groove (preferably with a V shape) in the surface of the above-mentioned wafer along the boundary lines of the above-mentioned semiconductor elements, exposes at least said groove, which has an opening width that is wider than the width of the dicing cut, and the end surfaces of the above-mentioned conductive supports, and covers the surface of the above-mentioned wafer with a resin; a process that arranges the above-mentioned external terminals on the end surfaces of the above-mentioned exposed conductive supports, and a process that dices the above-mentioned wafer along the boundary lines of the above-mentioned semiconductor elements.
In the process that covers the above-mentioned wafer surface with a resin, the resin also fills the groove formed in the wafer in advance. The wafer is diced at the position of the above-mentioned groove, and the resin in the groove covers part of the side surface of the corresponding diced semiconductor chips. As a result, the sealing reliability of the semiconductor device is improved.
Here, the process for covering the above-mentioned wafer surface with resin preferably also consists of a process that applies and cures the resin to the above-mentioned wafer surface in an approximately flat manner and a process that grinds the surface of the above-mentioned cured resin and exposes the end surfaces of the above-mentioned conductive supports.
With the grinding of the above-mentioned resin, the planarization of the resin surface including the end surfaces of the conductive support is easily achieved.
Also, a process for forming an elastic resin layer is preferably also done to the above-mentioned wafer surface before the process for forming the above-mentioned wiring.
An objective of the present invention is to provide a manufacturing method that improves the resin sealing reliability in a wafer-level CSP semiconductor device.
Another objective of the present invention is to provide a manufacturing method including a planarization process with high precision and favorable yield for a mounting surface in the above-mentioned semiconductor device.
REFERENCES:
patent: 5925931 (1999-07-01), Yamamoto
patent: 5977641 (1999-11-01), Takahashi et al.
patent: 6075280 (2000-06-01), Yung et al.
patent: 6235552 (2001-05-01), Kwon et al.
patent: 2000068405 (2000-03-01), None
Masumoto Kenji
Masumoto Mutsumi
Brady W. James
Dang Trung
Kebede Brook
Petersen Bret J.
Telecky , Jr. Frederick J.
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