Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-10-01
2002-10-01
Smith, Matthews (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06460174
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of designing an integrated circuit and a model for use in designing an integrated circuit.
BACKGROUND OF THE INVENTION
As integrated circuits become more complicated, it has become harder to translate an initial design into a silicon design. In principle it is possible for the silicon design to be drawn up by an individual. However in practice, this is difficult for an individual designer to do as there are a huge number of components on a chip. One small error in the design may result in a faulty integrated circuit. Additionally, this process is very slow and can significantly delay the amount of time taken to get the integrated circuit to the manufacturing stage.
Various computer programs have been proposed to assist in the design of an integrated circuit and more particularly in the testing of a design. These computer programs have typically been in the form of digital simulators which simulate a circuit under test. A hardware description language (HDL) has been designed to simulate and describe the behaviour of digital circuitry. However, whilst programs such as HDL are useful in testing a design, they do not assist in the design of the integrated circuit itself.
Additionally, once the higher level design of an integrated circuit has been completed, it can be a laborious process to obtain the gate level design which provides the higher level function.
SUMMARY OF THE INVENTION
It is therefore an aim of embodiments of the present invention to provide a method which is able to reduce the amount of time required in order to design an integrated circuit.
According to one aspect of the present invention, there is provided a method of designing an integrated circuit comprising at least one requester and at least one target, said at least one requester and at least one target being connected by a connection network, said method comprising the steps of:
defining at least one parameter for said at least one requester to model said requester;
defining at least one parameter for said at least one target to model said target;
defining connection information for said connection network to model said network; and
producing from said defined parameters and connection information implementation information for implementing said system.
According to a second aspect of the present invention, there is provided a model for use in designing an integrated circuit comprising at least one requester and at least one target connected by a connection network, said model comprising:
a requester model, one requester model being provided for each requester;
a target model, one target model being provided for each target; and
a connection network model, wherein at least one of the requester model, the target model and the connection model have has one or more parameters defining the behaviour of the respective model, at least one of said parameters being selectable.
REFERENCES:
patent: 4814981 (1989-03-01), Rubinfeld
patent: 5251311 (1993-10-01), Kasai
patent: 5386565 (1995-01-01), Tanaka et al.
patent: 5423050 (1995-06-01), Taylor et al.
patent: 5434804 (1995-07-01), Bock et al.
patent: 5440705 (1995-08-01), Wang et al.
patent: 5448576 (1995-09-01), Russell
patent: 5452432 (1995-09-01), Macachor
patent: 5455936 (1995-10-01), Maemura
patent: 5479652 (1995-12-01), Dreyer et al.
patent: 5483518 (1996-01-01), Whetsel
patent: 5488688 (1996-01-01), Gonzales et al.
patent: 5530965 (1996-06-01), Kawasaki et al.
patent: 5570375 (1996-10-01), Tsai et al.
patent: 5590354 (1996-12-01), Klapproth et al.
patent: 5596734 (1997-01-01), Ferra
patent: 5598551 (1997-01-01), Barajas et al.
patent: 5608881 (1997-03-01), Masumura et al.
patent: 5613153 (1997-03-01), Arimilli et al.
patent: 5627842 (1997-05-01), Brown et al.
patent: 5657273 (1997-08-01), Ayukawa et al.
patent: 5682545 (1997-10-01), Kawasaki et al.
patent: 5704034 (1997-12-01), Circello
patent: 5708773 (1998-01-01), Jeppesen, III et al.
patent: 5724549 (1998-03-01), Selgas et al.
patent: 5737516 (1998-04-01), Circello et al.
patent: 5751621 (1998-05-01), Arakawa
patent: 5768152 (1998-06-01), Battaline et al.
patent: 5771240 (1998-06-01), Tobin et al.
patent: 5774701 (1998-06-01), Matsui et al.
patent: 5778237 (1998-07-01), Yamamoto et al.
patent: 5781558 (1998-07-01), Inglis et al.
patent: 5796978 (1998-08-01), Yoshioka et al.
patent: 5828825 (1998-10-01), Eskandari et al.
patent: 5832248 (1998-11-01), Kishi et al.
patent: 5835963 (1998-11-01), Yoshioka et al.
patent: 5848247 (1998-12-01), Matsui et al.
patent: 5860127 (1999-01-01), Shimazaki et al.
patent: 5862387 (1999-01-01), Songer et al.
patent: 5867726 (1999-02-01), Ohsuga et al.
patent: 5884092 (1999-03-01), Kiuchi et al.
patent: 5896550 (1999-04-01), Wehunt et al.
patent: 5918045 (1999-06-01), Nishii et al.
patent: 5930523 (1999-07-01), Kawasaki et al.
patent: 5930833 (1999-07-01), Yoshioka et al.
patent: 5944841 (1999-08-01), Christie
patent: 5950012 (1999-09-01), Shiell et al.
patent: 5953538 (1999-09-01), Duncan et al.
patent: 5956477 (1999-09-01), Ranson et al.
patent: 5978874 (1999-11-01), Singhal et al.
patent: 5978902 (1999-11-01), Mann
patent: 5983017 (1999-11-01), Kemp et al.
patent: 5983379 (1999-11-01), Warren
patent: 6134516 (2000-10-01), Wang
patent: 0165600 (1991-11-01), None
patent: 0636976 (1995-02-01), None
patent: 0636976 (1995-02-01), None
patent: 0652516 (1995-05-01), None
patent: 0702239 (1996-03-01), None
patent: 0720092 (1996-07-01), None
patent: 0933926 (1999-08-01), None
patent: 0945805 (1999-09-01), None
patent: 0959411 (1999-11-01), None
patent: PCT/JP96/02819 (1996-09-01), None
patent: 8320796 (1996-12-01), None
patent: 8329687 (1996-12-01), None
patent: 9212358 (1997-08-01), None
patent: 9311786 (1997-12-01), None
patent: 10106269 (1998-04-01), None
patent: 10124484 (1998-05-01), None
patent: 10177520 (1998-06-01), None
Richard York; Real Time Debug for System-on-Chip Devices; Jun. 1999, pp. 1-6.
Do Thuan
Munck William A.
Smith Matthews
STMicroelectronics Ltd.
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