Electrical computers and digital processing systems: processing – Processing control – Arithmetic operation instruction processing
Reexamination Certificate
1999-10-04
2002-10-01
Kim, Kenneth S. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Arithmetic operation instruction processing
C708S204000, C708S513000, C712S222000
Reexamination Certificate
active
06460135
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a microprocessor and a LSI (Large Scale Integrated circuit) in which the microprocessor is integrated as a core, and in particular, to a microprocessor which contains a general-purpose register (hereinafter, referred to as a register) and a LSI in which the microprocessor is integrated as a core.
All of registers provided inside a microprocessor generally have fixed bit widths. In this case, when there is not in agreement with an effective bit width of a real data, for example, when the effective bit width of the real data is smaller than the bit width of the register, an upper bit of the register is invalid.
The effective bit width of the data retained in the register is set by an instruction which conducts data-load for the register. To this end, compiler for use in the microprocessor must assure matching between the bit width of the register of the microprocessor and the effective bit width of the real data.
Meanwhile, the bit width of the register of the microprocessor trends to extend every when generation of the processor is updated. The bit width has been extended at every double as 8 bits, 16 bits, 32 bits, 64 bits, and 128 bits.
On the other hand, the microprocessor assures host compatibility at a binary level in many cases in order to utilize past software source. In principle, design is performed such that past program itself can be executed (for example, refer to Japanese Unexamined Patent Publication (JP-A) No. S63-5432).
However, when the bit width of the register is extended in the above-mentioned conventional microprocessor, no consideration is taken about a bit of the extended portion in the past program. Therefore, there is possibility that inconvenience with respect to software occurs. In particular, this trend readily occurs when an instruction is optimized for the microprocessor of a specific generation.
Further, a data type of a data retained in the register includes a fixed decimal point type, a floating decimal point type, a vector type except an integral number type specified by the effective bit width, and control and conversion of these data types are complex under control of the compiler.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide a microprocessor which is capable of assuring an operation of a program even when a bit width of a register is varied by bit width extension due to generation change of the microprocessor.
It is another object of this invention to provide a microprocessor which is capable of previously preventing generation of bug due to an error of a data type which becomes a problem at an initial stage of program development.
It is further another object of this invention to provide a LSI which contains the above-mentioned microprocessor as a core.
In a microprocessor according to this invention, a type information register is attached to an internal data register, and a type information (a data type and an effective bit width) of a data retained in a data resister is indicated.
The type information register is updated with reference to the type information of the data at a time of execution of a load instruction from a memory into the register or storage of a calculation result. When a variety of instructions are executed for the register and when the data is read out from the register, the type information is also read out with the data, and is sent to an internal bus with a variety of control information.
A calculation execution unit detects the type information, and designates the type information contained in the instruction, or compares with the type information of the other data. When disagreement occurs for the type information of each data, the type of the data is automatically converted, or matching is realized by software by generating an exception interruption.
Thereby, the instruction itself can conduct a process without considering the type information of the data sent from the register.
REFERENCES:
patent: 6105129 (2000-08-01), Meier et al.
patent: 6108772 (2000-08-01), Sharanpani
patent: 6170001 (2001-01-01), Hinds et al.
patent: 6195746 (2001-02-01), Nair
patent: 63-5432 (1988-01-01), None
patent: 1-307831 (1989-12-01), None
patent: 5-100854 (1993-04-01), None
patent: 5-324313 (1993-12-01), None
patent: 8-16391 (1996-01-01), None
Japanese office Action dated Mar. 24, 2000 with partial translation.
Kim Kenneth S.
McGinn & Gibb PLLC
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