Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-02-18
2002-11-05
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06477690
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains generally to interconnect routing in integrated circuit design, and more particularly to a method for inserting in-place interconnect repeaters along over-the-block interconnect paths in integrated circuits.
BACKGROUND OF THE INVENTION
Integrated circuits comprise a plurality of electronic components that function together to implement a higher-level function. ICs are formed by implanting a pattern of transistors into a silicon wafer which are then connected to each other by layering multiple layers of metal materials, interleaved between dielectric material, over the transistors. The fabrication process entails the development of a schematic diagram that defines the circuits to be implemented. A chip layout is generated from the schematic. The chip layout, also referred to as the artwork, comprises a set of planar geometric shapes over several layers that implement the circuitry defined by the schematic. A mask is then generated for each layer based on the chip layout. Each metal is then successively manufactured over the silicon wafer according to the layer's associated mask using a photolithographical technique.
The process of converting the specifications of an electrical circuit schematic into the layout is called the physical design process. CAD tools are extensively used during all stages of the physical design process. The physical design process is accomplished in several stages including partitioning, floorplanning, and routing.
During the partitioning stage, the overall integrated circuit is partitioned into a set of functional subcircuits called blocks. The block partitioning process considers many factors including the number and size of the blocks, and number of interconnections between the blocks. The output of partitioning is a set of blocks along with a set of interconnections required between blocks, referred to herein as a netlist.
During the floorplanning stage, a floorplan is developed defining the placement and rectangular shape of each block. The goal of the floorplanning stage is to select the optimal layout for each block, as well as for the entire chip.
Once an acceptable floorplan is developed, the interconnections between the blocks (as defined by the netlist) are routed. The space not occupied by the blocks is partitioned into rectangular regions referred to as channels. Interconnects are preferably routed within the designated channels, but may also be routed through defined feedthroughs through the blocks, or in defined over-the-block routing space.
The goal of a router is to complete all circuit connections resulting in minimal interconnect signal delay. Where possible, the router will generally attempt to route individual interconnects on a single layer; however, if this is not achievable given the topology of the netlist, an interconnect may be routed over two or even more layers. Often, interconnect routes resulting from the autorouting will be too long to meet signal delay specifications. The delay results from the inherent RC characteristics of the interconnect line. Signal transition time can often be significantly improved by introducing one or more signal repeaters along the path of the interconnect line.
Over the past decades, integrated circuits (ICs) of increasingly higher density have been developed to meet industry demands of higher performance and smaller packaging. The very high densities of today's integrated circuits means that more metal layers and interconnects per layer are required than ever before. The result is that the routing task has become even more complex, often resulting in a higher number of interconnects that do not meet the timing criteria, and therefore an increasingly higher number of required repeaters. When over-the-block routing is employed, the insertion of repeaters along the over-the-block interconnects is problematic due to the need to be able to connect from the metal layer on which the problem interconnect resides, through any intervening layers, to the repeaters ports.
On previous channel-routed ICs, the conventional process for inserting repeaters involved the process of routing the interconnects without insertion of repeaters, extracting the timing for the interconnects, determining the placement of repeaters to improve unacceptable timing paths (usually by simulating with a CAD tool such as SPICE), and adding the repeaters one at a time to the schematic and artwork to create a new netlist. The new netlist was then resubmitted to the router and the process repeated. It will be noted that the second route (with repeaters) typically results in a routing solution that is quite different from the initial route, and therefore often contains unacceptable net propagation delays due to the re-route. In other words, the optimal repeater solution for the initial route will not necessarily be the optimal repeater solution for the second route. Accordingly, the rip-up and re-route process is typically repeated, feeding the router the netlist generated on the previous iteration of the process, until all interconnects satisfactorily meet the timing criteria. Because the previous routing solution is not preserved when the router routes the new netlist, this process is often referred to as “rip-up and re-route”.
Importantly, as just described, new repeaters are added to the netlist and schematic on each iteration of the process. Each time a repeater is added to the schematic, two separate new nets replace the original net, one of which connects to the input port of the repeater, and the other of which connects to the output port of the repeater. Accordingly, it will be appreciated that the number of nets and number of connections that the router must route increases by at least two for each repeater inserted. Because the updated netlist with the additional nets and connections is then resubmitted to the router in the prior art, the routing problem faced by the router becomes more complex for each successive iteration of the rip-up and re-route process. For example, suppose the original netlist comprises 15K nets and 30K connections. If after the first iteration the router determines that each net requires one repeater, the new netlist will comprise twice the number of nets and connections (30K nets and 60K connections) as the original netlist. It is clear that the routing problem submitted to the router becomes increasingly difficult on each iteration of the rip-up and re-route process as the netlist gets updated to accommodate new repeaters on each iteration.
It is therefore and object of the invention to eliminate the iterative rip-up and re-route process by providing a methodology for allowing in-place insertion of repeaters along an interconnect.
SUMMARY OF THE INVENTION
The present invention is a novel method and system for inserting in-place interconnect repeaters along over-the-block interconnect paths in integrated circuits. In accordance with the invention, the over-the-block interconnects are routed without repeaters but with some metal reserved for repeater stitching on each intervening layer between the interconnect layer and repeater ports. The ideal number and locations of repeaters for each net which will result in the minimized propagation delay and acceptable signal transition timing are then calculated, considering only those places where the routed signal passes over a pre-determined legal repeater area. The calculated repeaters are stitched into the existing route artwork using the metal previously reserved for repeater stitching, and the repeaters are added to the schematic.
Because only locations where interconnects pass over legal repeater areas are considered, the method of the invention avoids the traditional rip-up and re-route method, thereby simplifying the routing problem submitted to the router, and reducing the time required to reach an acceptable routing solution.
REFERENCES:
patent: 5196362 (1993-03-01), Suzuki
patent: 5654898 (1997-08-01), Roetcisoender et al.
patent: 5838538 (1998-11-01), Srivatsa
patent: 5859999 (
Dixon Daniel J
Witte Jeffrey P
Hewlett--Packard Company
Lin Sun James
Siek Vuthe
LandOfFree
In-place repeater insertion methodology for over-the-block... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with In-place repeater insertion methodology for over-the-block..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and In-place repeater insertion methodology for over-the-block... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2983628