Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – Having specific type of active device
Reexamination Certificate
2000-08-25
2002-10-29
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
Having specific type of active device
C257S208000, C438S128000, C438S129000
Reexamination Certificate
active
06472696
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention lies in the semiconductor technology field. More specifically, the present invention relates to a memory cell configuration having a large number of memory cells provided in a semiconductor substrate and having bit-line trenches which extend in parallel in the longitudinal direction in the main face of the semiconductor substrate. A first conductive region is provided at the bottoms of the bit-line trenches and a second conductive region of the same conductivity type as the first conductive region is provided at the peaks of each of the bit-line trenches. An intermediately located channel region is provided in the walls in each case. Word lines extend in the transverse direction along the main face of the semiconductor substrate through specific bit-line trenches to activate transistors provided there.
Although it can be used on memories made of any desired base material, the present invention and the problem on which it is based will be explained with reference to a memory based on silicon.
Early memory cell configurations were predominantly based on planar concepts. With the predefinition of a continuously increasing packing density, it was proposed, initially for mask ROM applications (read-only memories) and subsequently for memories with optional access (RAM memories) to fold the cell area of the memory by means of the introduction of parallel longitudinal trenches, and therefore to produce the projection of the cell area onto the wafer surface by up to 50%.
Commonly assigned U.S. Pat. No. 5,920,099 (German patent application DE 195 10 042) discloses a read-only memory cell configuration in which the memory cells are arranged in lines which extend in parallel. Longitudinal trenches are provided which extend essentially parallel to the lines. There, the lines are arranged in each case alternately on the main face between adjacent longitudinal trenches and on the bottom of the longitudinal trenches. Isolation structures are provided for the mutual isolation of the memory cells, which each comprises an MOS transistor. Extending transversely to the lines are word lines, which are each connected to the gates of MOS transistors arranged in different lines. In that case, the minimum theoretical space requirement for each memory cell is 2·F
2
, where F is the minimum structure size of the respective technology.
Commonly assigned U.S. Pat. No. 5,920,778 (German patent application DE 195 14 834) discloses a read-only memory cell configuration which has first memory cells with a vertical MOS transistor and second memory cells without a vertical MOS transistor. The memory cells are arranged along opposite flanks of strip-like isolation trenches which extend in parallel. If the width and spacing of the isolation trenches are selected to be equal in size, the minimum space requirement for each memory cell is theoretically 2 F
2
, where F is the minimum structure size of the technology.
The problem on which the present invention is based is that, in such cell configurations having line regions which extend in parallel with the longitudinal trenches, alternately on the peaks of the trenches and the bottoms of the trenches, the word lines extending perpendicular thereto at a specific spacing from one another, the silicon on the trench walls between the word lines is not covered by gate electrodes. If charges are present in the isolation oxides, spacer oxides or other layers which are deposited in front of them in the further production process, it is possible for a channel to be formed there, which leads to unacceptable leakage currents between the conductive regions on the peaks of the trenches and the bottoms of the trenches.
Attempts have been made to solve this problem by providing a high basic doping level of the silicon in the cell field. However, this usually has disadvantageous effects on the vertical components. In addition, attempts have been made to minimize the charge density in the oxides, which makes the corresponding processes more expensive and cannot be reliably controlled from the start.
SUMMARY OF THE INVENTION
The object of the invention is to provide a memory cell configuration an a production method which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this kind, and which enables simple and reliable production and allows the leakage currents to be reduced considerably without a relatively large process outlay.
With the above and other objects in view there is provided, in accordance with the invention, a memory cell configuration, comprising:
a semiconductor substrate having a main face and defined longitudinal and transverse directions;
a multiplicity of memory cells formed in the semiconductor substrate;
a plurality of mutually parallel bit-line trenches extending in the longitudinal direction in the main face of the semiconductor substrate, the bit-line trenches having bottoms each formed with a first conductive region, peaks each formed with a second conductive region of a same conductivity type as the first conductive region is provided, and walls with a respective intermediately located channel region; and
word lines extending in the transverse direction along the main face of the semiconductor substrate, through specific the bit-line trenches, for activating transistors formed in the specific bit-line trenches; and
additional dopant introduced in the trench walls of the bit-line trenches located between the word lines, for increasing a corresponding transistor turn-on voltage to suppress leakage currents.
By comparison with the prior art memory cell configurations, the memory cell configuration according to the invention has the advantage that the leakage currents at the relevant trench walls can be reduced considerably without the process being significantly more complicated. In the production process according to the invention, the vertical components are essentially protected by the word lines that have already been applied, if it is ensured that the implantation direction lies in a plane which passes essentially perpendicularly through the center of the word lines. In other words, the implantation direction should be selected such that, in essential terms, no dopant can pass under the word lines into the vertical components, that is to say transistors, already produced. In addition, if appropriate, sensitive peripheral or planar components should be protected.
In general terms, the idea on which the present invention is based is that an additional dopant is introduced into the trench walls of the bit-line trenches which are located between the word lines, in order to increase the corresponding transistor turn-on voltage there to suppress leakage currents.
In accordance with a preferred embodiment of the invention, the memory cell configuration is a read-only memory with cells having a cell size of 2F
2
, where F is a minimum structure width.
In accordance with an added feature of the invention, the memory cells are each arranged on opposite walls of the bit-line trenches.
In accordance with an additional feature of the invention, the memory cells include first memory cells storing a first logic value and having at least one vertical transistor, and second memory cells storing a second logic value and not having a vertical transistor.
With the above and other objects in view there is also provided, in accordance with the invention, a method of producing a memory cell configuration, such as the assembly according to the above summary. The method comprises the following steps:
providing a semiconductor substrate;
forming a multiplicity of bit-line trenches in a main face of the semiconductor substrate;
forming first conductive regions on respective bottoms of the bit-line trenches and second conductive regions on peaks of the bit-line trenches;
forming transistors at specific locations in the respective bit-line trenches;
forming the word lines; and
introducing additional dopant into trench walls extending between the word lines, for increasi
Böhm Thomas
Hain Manfred
Kohlhase Armin
Otani Yoichi
Rusch Andreas
Flynn Nathan J.
Infineon - Technologies AG
Wilson Scott R.
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