Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-12-08
2002-12-17
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S189040, C365S230050
Reexamination Certificate
active
06496432
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a method and apparatus for testing in general, and in particular to a method and apparatus for testing memory cells. Still more particularly, the present invention relates to a method and apparatus for testing a write function of a dual-port static memory cell.
2. Description of the Prior Art
A dual-port memory cell typically consists of a static memory element and a set of access devices. In most applications, the static memory element is a pair of cross coupled inverters, and the access devices are N-channel transistors. Each port of the dual-port memory cell is associated with a pair of true and complement bitlines. The true side of the static memory element is connected to each true bitline via a respective access device, and the complement side of the static memory element is connected to each complement bitline via a respective access device. The bitlines carry data to or from the static memory element when the memory cell is being written or read.
All dual-port static memory cells are capable of having both a write cycle and a read cycle occurring simultaneously at separate ports of a same memory cell. Importantly, most, if not all, dual-port static memory cells are guaranteed by their manufacturers to have a successful data write operation during the above-mentioned concurrent read/write cycle at the same memory cell. The present disclosure provides a method and apparatus for testing a write function of a dual-port static memory cell during a concurrent read/write cycle on a memory cell.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the present invention, a memory cell of a multi-port memory is read via a first port of the memory cell. After the read operation, the standard bitline restore operation that normally occurs after a read or write operation is suppressed from occurring on the bitlines for the first port. Then, the memory cell is read again via the first port at the same time the memory cell is being written via a second port with a logical data value that is opposite to the logical data value being read from the first port. After the completion of the write operation, the bitlines for the first and second ports are restored by a bitline restore operation. Finally, the logical data value in the memory cell is verified for its correctness.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 4817051 (1989-03-01), Chang
patent: 5579322 (1996-11-01), Onodera
patent: 5734613 (1998-03-01), Gibson
patent: 5742557 (1998-04-01), Gibbins et al.
patent: 5796745 (1998-08-01), Adams et al.
patent: 5825782 (1998-10-01), Roohparvar
patent: 5896330 (1999-04-01), Gibson
patent: 5973985 (1999-10-01), Ferrant
patent: 5987632 (1999-11-01), Irrinki et al.
patent: 6288969 (2001-09-01), Gibbins et al.
Ouellette Michael Richard
Rowland Jeremy Paul
Wager David Jerome
Bracewell & Patterson L.L.P.
Henkler Richard A.
Zarabian A.
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