Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-06-22
2002-10-08
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06463569
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data processing method for designing a layout of a large scale integrated (LSI) circuit and a recording medium incorporating therein a program for such data processing. More particularly, the present invention relates to a data processing method for calculating and storing in a memory to deform a data structure of layout designing data in which cells having geometry information and also having reference information to refer to geometry information of other cells are hierarchically combined with each other.
2. Description of the Related Art
Data for designing a physical layout for designing LSI are composed in such a manner that data, which are referred to as cells, are hierarchically combined with each other. Each cell has geometry information and reference information used for referring to geometry information of another cell. In the case where a photo-mask or printed board is manufactured by using such layout designing data, in order to conduct logical operations (different logical operations include such ones as OR, AND, XOR, NOT, SUB, and positive- and negative-resizing) between the figures of the cells, the hierarchical structure is collapsed, that is, the hierarchical structure is deformed to be a flat structure, and the calculation is conducted.
Each cell C is composed of geometry information “f”, which is directly owned by the cell concerned, and also composed of reference information (s, a) for referring to another cell. The relation between these pieces of information is expressed by the following expression (1).
C=f+
(
s, a
) (1)
In the above expression, “s” indicates that the geometry information “f” of another cell is simply referred to once, that is, “s” includes a piece of positional information for directing movement, rotation and reflection of geometry information “f”. In the above expression, “a” indicates that geometry information “f” to be referred to should be referred to as two-dimensional array arrangement of n columns and m rows. Note that “s” and “a” can be applied not only to “f” but also to “s” or “a” of another cell.
In short, cascading hierarchical reference can be represented by arbitrary multiplication of “s” and “a”. In this case, the reason why “f” is expressed by a bold letter is that “f” can be generally processed as a vector composed of a plurality of polygons. The reason why “(s, a)” are expressed by bold letters is that “(s, a)” can be processed as vectors having a position (direction) and intensity (quantity of data).
FIG. 4
is a view schematically showing a model of the composition in which a plurality of cells compose one set of layout designing data, which are correlated with each other, in a hierarchical structure.
FIG. 4
is interpreted as follows. (1) Cell C
0
refers to cell C
1
by the arrangement of al. Also, cell C
0
refers to cell C
2
by the arrangement of a
2
. At this time, cell C
0
is not referred by any other cell. Therefore, cell C
0
is referred to as “top cell Ct”.
(2) Cell C
1
singly refers to cell C
3
by S
1
, S
2
, S
3
and S
4
, that is, cell C
1
singly refers to cell C
3
four times in total. Further, cell C
1
singly refers to cell C
4
by S
5
.
(3) Cell C
2
refers to cell C
3
by a
3
. Cell C
2
refers to cell C
4
by a
6
. Cell C
2
singly refers to cell C
4
by s
6
and s
7
two times in total.
(4) Cells C
3
and C
4
are referred to by other cells and do not refer to other cells by themselves. Therefore, cells C
3
and C
4
are referred to as atom cells Ca.
The above relations are expressed by the following expression (2).
C
0
=
f
0
+
a
1
C
1
+
a
2
C
2
C
1
=
f
1
+
s
1
C
3
+
s
2
C
3
+
s
3
C
3
+
s
4
C
3
+
s
5
C
4
C
2
=
f
2
+
a
3
C
3
+
a
6
C
4
+
s
6
C
4
+
s
7
C
4
C
3
=
f
3
C
4
=
f
4
(2)
Conducting operation (OR processing) by collapsing the hierarchical structure is the same as expressing top cell Ct=C
0
only by f, s and a. When expression (2) is actually expanded, the following expression (3) can be obtained, the right side of which is composed of 12 terms. In this connection, the sign + expresses that the developed geometry information must be subjected to OR operation.
C
0
=
f
0
+
a
1
f
1
+
a
2
f
2
+
a
1
s
1
f
3
+
a
1
s
2
f
3
+
a
1
s
3
f
3
+
a
1
s
4
f
3
+
a
1
s
5
f
4
+
a
2
a
3
f
3
+
a
2
a
6
f
4
+
a
2
s
6
f
4
+
a
2
s
7
f
4
(3)
In expression (3), when not less than two operators act on f as shown by a
2
a
3
f
3
, the operators act in the order of closeness to f. That is:
a
2
a
3
f
3
=(
a
2
(
a
3
f
3
))
Therefore, f
3
is referred by the arrangement of a
3
. The result is referred by the arrangement of a
2
. In this connection, the commutative law of operators is not established. That is:
aiajf≠ajaif
(
ai≠aj
)
The actual layout designing data is complicated in many cases. Therefore, it is not unusual that the number of terms on the right side of the expression (3) exceeds one million. An OR operation is conducted after these terms have been classified by a spatial positional relation. Therefore, it is necessary that all these terms are stored in the memory. That is, when the number of the terms on the right side of the expression (3) is large, the memory requirement for computation must be increased. Accordingly, it takes a long operation time and, further the manufacturing cost is increased.
SUMMARY OF THE INVENTION
The present invention has been accomplished to solve the above problems of the prior art.
It is an object of the present invention to provide a data processing method and a recorded medium incorporating therein a program capable of reducing the operation processing time by deforming and simplifying the data structure of layout designing data composed of cells which are hierarchically combined with each other.
In order to solve the above problems, the present invention is composed as follows.
The present invention provides a method of data processing for calculating and storing in a memory so as to deform a data structure of layout designing data in which cells having geometry information of the cells concerned and also having reference information to refer to geometry information of another cell are hierarchically combined with each other, the method of data processing being characterized in that: cell Cx of an upper layer for referring to atom cell Ca, cell Ca having only geometry information and not referring to geometry information of a lower layer by itself, is made to have the geometry information of atom cell Ca by copying; reference information of cell Cx is deleted and cell Cx is replaced with C′x; cell Cy of an upper layer, which refers to geometry information of cell C′x concerned, is made to have geometry information of cell C′x by copying; reference information of cell Cy is deleted and cell Cy is replaced with cell C′y; and the above operation is repeated so that the data structure hierarchically combined from the top cell Ct of the uppermost layer, which is not referred by any other cell, to the atom cell Ca of the lowermost layer, is deformed and stored.
In this case, it is preferable that only when a quantity g of data obtained from geometry information and reference information of cells Cx, Cy, . . . , which refer to the cells of a lower layer including atom cell Ca, is not more than threshold value w which is set for each hierarchy to which each cell Cx . . . Cy, belongs, geometry information of the lower layer cell is made to copy on geometry information of each cell Cx, Cy, and reference information is deleted and each cell Cx, Cy is replaced with C′x, C′y, . . .
According to another aspect of the present invention is to provide a recorded medium incorporating therein a program to carry out the above-mentioned method.
REFERENCES:
patent: 5459827 (1995-10-01), Allouche et al.
patent: 5473546 (1995-12-01), Filseth
patent:
Shinko Electronic Industries Co., Ltd.
Siek Vuthe
Staas & Halsey , LLP
Thompson A. M.
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