Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2001-06-06
2002-10-08
Lee, Eddie (Department: 2815)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S149000, C438S151000, C438S197000, C438S294000
Reexamination Certificate
active
06461903
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method for fabricating a SOI device, and more particularly to a method for fabricating a part depletion type SOI device capable of preventing mis-operation of a circuit due to a floating body effect.
2. Description of the Related Art
With high performance of semiconductor devices, the semiconductor integration technology using SOI wafer having a stack structure of a buried oxide film sandwiched between a base substrate and a semiconductor layer instead of single crystal silicon wafer being comprised of a bulk silicon has been proposed. It is because the devices fabricated into the SOI wafer have advantages of high speed due to a low junction capacitance and latch-up reduction due to a complete device isolation as compared with those fabricated in the single crystal silicon wafer.
The SOI devices are classified into a full depletion type device and a part depletion type device according to the thickness of the semiconductor layer.
In the full depletion type devices, the body of transistor, that is, the part of the semiconductor layer that the channel is to be formed, is thicker than the field oxide film. However, in the part depletion type device, the body of transistor is as thick as the field oxide film.
In the part depletion type SOI device, since the body of a transistor is fully isolated by the field oxide film and buried oxide film, mis-operation is generated by a floating body effect. Accordingly, the operation performance becomes unstable.
In more detail, as shown in
FIG. 1
, the part depletion type SOI device has the structure that the body of a transistor, that is, the semiconductor layer
3
where the channel is to be formed, is fully isolated by a buried oxide film
2
and a field oxide film
4
. In the structure, a hole generated by impact ionization due to high electric field in the drain region
8
is accumulated on the neutral layer of source region
7
having the lowest energy, that is, a boundary with channel region
3
. However, the hole accumulated on the neutral layer of the source region
7
decreases the threshold voltage and generates kink phenomenon that is an instantaneous increase of drain electric current by turning on the PN junction interposed between the channel region
3
and the source region
7
. Accordingly, the part depletion type SOI devices have unstable operation performance by a parasitic bipolar transistor and the floating body effect such as the kink phenomenon. Therefore, in order to ensure a stable operation performance, it is required to remove the floating body effect.
In the
FIG. 1
, reference numeral
1
denotes a base substrate, reference numeral
5
denotes a gate insulating film, and reference numeral
6
denotes a gate electrode.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method for fabricating part depletion type SOI devices capable of removing the floating body effect.
According to an aspect of the present invention, there is provided to a method for fabricating a SOI device comprising: preparing a SOI wafer having a stack structure of a base substrate, a buried oxide film, and a semiconductor layer; forming a field oxide film on the semiconductor layer to define an active region; forming a gate on the active region of the semiconductor layer; forming a dummy spacer on the gate and both side walls thereof; forming a polycrystalline silicon film at a selected width on the both sides of gate including the dummy spacer; depositing an insulating film over the resultant structure; polishing the insulating film using a dummy spacer as a polishing stop layer; removing the polycrystalline silicon layer to expose a part of the semiconductor layer; forming a hole exposing a part of the buried oxide film by dry etching the exposed part of the semiconductor layer; etching the buried oxide film exposed through the hole and the area adjacent thereto using a wet etching process; growing a silicon epitaxial layer from the midpoint of the semiconductor layer to the point higher than the upper surface of the semiconductor layer on the side of the semiconductor layer exposed through the hole using the selective epitaxial growth process; etching the surface of the silicon epitaxial layer to be equivalent to the height of the semiconductor layer; removing the dummy spacer and the insulating film; and forming source/drain regions of LDD structure having the physical isolation space on the boundaries between source/drain regions and a channel region in the active region of the exposed semiconductor layer.
The above objects and other features and advantages of the present invention will become more apparent in light of the following detailed description and the accompanying figures.
REFERENCES:
patent: 5405795 (1995-04-01), Beyer et al.
patent: 5726081 (1998-03-01), Lin et al.
patent: 5923980 (1999-07-01), Gardner et al.
patent: 6048756 (2000-04-01), Lee et al.
patent: 6110769 (2000-08-01), Son
patent: 6365445 (2002-04-01), Yu
patent: 6376285 (2002-04-01), Joyner et al.
Hynix / Semiconductor Inc.
Lee Eddie
Richards N. Drew
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