Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2001-02-26
2002-06-04
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S189120, C365S063000, C365S195000, C365S185170, C365S185220, C365S185030
Reexamination Certificate
active
06400624
ABSTRACT:
BACKGROUND
The present invention relates generally to memory devices. More particularly, the present invention relates to a descending staircase read technique for a multi-level cell NAND flash memory device.
A variety of semiconductor memory devices have been developed for storage of information. Examples include volatile and nonvolatile memory. Nonvolatile memory provides a key advantage in that it retains stored data after power is removed from the device. One example of nonvolatile memory is flash memory. However, manufacture and operation of nonvolatile memory is generally more complex than for volatile memory. For all memory devices, important design goals include increased storage density and reduced read and write times.
A conventional memory device includes an array of storage cells or memory cells. Each cell stores a single binary digit or bit of information. For example, in a flash memory, the threshold voltage of a transistor in the memory cell is adjusted according to the data stored. During a read cycle, the threshold voltage is sensed to resolve the state of the data stored. In a conventional binary memory, this data is conventionally described as having a state of logic 0 or logic 1. The array of storage cells is surrounded by circuits for reading and writing data and controlling operation of the memory device.
Recently, multi-level cell memories have been developed. Multi-level storage refers to the ability of a single memory cell to store or represent more than a single bit of data. A multi-level cell may store 2, 4, 8 . . . etc., bits in a single storage location. Multi-level storage is achieved by storing charge on a floating gate of a memory cell to establish a threshold voltage Vt level for the cell from among three or more possible threshold voltages. The actual Vt produced will fall within a program distribution with some allowed tolerance still providing reliable operation.
In any memory, there are several internal parameters can affect program distributions. Examples include: program pulse count, or the number of signal pulses that must be applied to a memory cell to program the cell to a selected level; program pulse width, or the time duration of signal pulses which program the cell; read verify reference current, or the current used as a reference when resolving the stored state of the memory cell; program inhibit voltage and read pass voltage. Such parameters are referred to herein as performance variables, although once established they may not vary but instead remain constant.
All of these performance variables and more can be tuned to optimize reading, writing and verifying performance of the memory device. Optimization is required because of variations in device performance as a result of manufacturing tolerances and because of product variation over the lifetime of the product. Optimization may be required at various times over the operating life of the memory device. Initial optimization based on simulation and design is hard wired using metallization of the memory integrated circuit.
In conventional devices, two techniques have been used to generate these various settings. The first technique involves metal options for the integrated circuit. Metal masks may be changed or the silicon connections may be post-processed after most or all of the conventional masking steps to optimize performance variables. These metal option methods are time consuming and are generally not reversible, so that re-optimization later is not possible. There is no test flexibility with these metal options, so that a performance variable may be programmed once at one test condition (operating voltage, temperature, etc.) with no opportunity to adjust the performance variable at another test condition. Many memory devices must be prepared and tested to examine interaction of variables. With a large number of performance variables, it is impossible to investigate a full design matrix.
A second technique has been used to generate performance variables in flash memory devices involves the use of content addressable memory or CAM cells consisting of a single flash memory cell. CAM cells are flexible and may be repeatedly programmed and erased, overcoming the chief limitation of metal options. However, CAM cells introduce a significant die size penalty. Each CAM cell must have its own high voltage circuit to generate the necessary program and erase voltages. Further, programming and erasing of memory cells requires significant time and increases testing complexity. In conventional designs, all CAM cells are erased together, meaning that the old state must be stored to return to default settings.
Accordingly, there is a need for an improved method for storing and updating performance variables in an integrated circuit such as a flash memory device.
BRIEF SUMMARY
By way of introduction only, a method for testing a multi-level memory includes storing multi-level data in a plurality of memory cells of the multi-level memory and reading from configure registers initial values of a plurality of performance variables. The performance variables set operating parameters of the multi-level memory. The method further includes during a first test phase operating the multi-level memory at the initial values of the plurality of performance variables and reading program values of the plurality of performance variables. During a second test phase, the multi-level memory is operated at the program values of the plurality of performance variables.
The foregoing discussion of the preferred embodiments has been provided only by way of introduction. Nothing in this section should be taken as a limitation on the following claims, which define the scope of the invention.
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James Eldridge, “Filing in a Flash”, IEEE Spectrum, Oct. 1993, pp. 53-54.*
“Flash Memory Goes Mainstream”, Dipert et al, Intel Corp., IEEE Spectrum Oct. 1993, pp. 48-52.
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Parker Allan
Skrovan Joseph
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