Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-03-06
2002-02-26
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S368000, C257S351000, C257S374000, C257S506000, C257S510000, C257S513000, C257S524000
Reexamination Certificate
active
06351014
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor devices and a method of manufacturing the same, and more particularly, a semiconductor device formed on an SOI (Silicon on Insulator) substrate in order to implement high speed operation and a method of manufacturing the same.
2. Description of the Background Art
Referring to
FIGS. 75
to
77
, description will be given of a plan structure and a sectional structure of a semiconductor device having a gate array, having a plurality of gates disposed thereon, formed on a silicon substrate.
At a prescribed position of a silicon substrate
316
, formed is a field oxide film
302
. Silicon substrate
316
includes a p type MOS field effect transistor forming region
310
, and an n type MOS field effect transistor forming region
312
formed therein. Gate electrode
304
are disposed regularly in respective MOS field effect transistor forming regions
310
,
312
. In a semiconductor device including a gate array structure as described above, respective blocks in which gate electrodes
304
are disposed are electrically isolated from each other by field oxide film
302
. In one block, active regions are electrically isolated by gate electrode
304
.
Referring to
FIG. 78
, the operational principle of isolation of transistors by an electrode will be specifically described, taking n type MOS field effect transistor forming region
312
as an example. By fixing gate electrode
304
to a ground potential, for example, a transistor
317
formed of a gate electrode
318
, a source region
320
and a drain region
322
, and a transistor
323
formed of a gate electrode
324
, a source region
326
and a drain region
328
are electrically isolated from each other. These transistors can operate independently. In p type MOS field effect transistor forming region
310
, by fixing to the power supply potential gate electrode
304
between transistors to be isolated, the similar effects can be obtained.
As described above, a method for electrically isolating transistors by fixing a gate electrode between the transistors to be isolated to the power supply potential or the ground potential is called a gate isolation method. The gate electrode between the transistors is called a gate isolation gate electrode. The gate isolation method is suitable for high integration as compared to an isolation method using a field oxide film, because the gate electrode can effectively be used in the former method.
Description will now be given of a semiconductor device configuring a 3-input NAND gate using the above-described gate isolation method with reference to
FIGS. 79 and 80
.
FIG. 80
is a plan view of the semiconductor device configuring a 3-input NAND gate shown in (a), (b) of FIG.
79
. In
FIG. 80
, the upper block corresponds to a p type MOS field effect transistor forming region, and the lower block corresponds to an n type MOS field effect transistor forming region. By configuring a gate electrode and a source/drain region in an internal interconnection structure as shown in
FIG. 80
, a 3-input NAND gate can be easily configured. In
FIG. 80
, by fixing the rightmost gate electrode of the p type MOS field effect transistor forming region and the rightmost gate electrode of the n type MOS field effect transistor forming region to the power supply potential and the ground potential, respectively, these forming regions can be electrically isolated from the other adjacent transistors.
A semiconductor device having a conventional gate array having a plurality of gates disposed therein, which is described above, is formed on a bulk silicon substrate. Formation of such a semiconductor device on an SOI (Silicon on Insulator) substrate is currently studied. If a CMOS (Complementary Metal-Oxide Semiconductor) field effect transistor is formed on an SOI substrate, the following features can be obtained as compared to a CMOS field effect transistor formed on a bulk silicon substrate:
(1) Increase in drivability
(2) Reduction of junction capacitance in source/drain region
(3) Latchup free
FIGS. 81 and 82
show cross sections in the case where MOS field effect transistors are formed on a bulk silicon substrate and an SOI substrate, respectively. In the case of the transistor fabricated on the SOI substrate, a depletion layer under a channel extends only to a buried oxide film. Therefore, a voltage applied to a gate electrode effectively generates carriers in the channel, resulting in increase of drivability. Since a source/drain junction is formed only in a surface perpendicular to an SOI layer because of the buried oxide film, the junction capacitance in the source/drain region can be reduced. Since respective MOS field effect transistors are electrically isolated completely by the buried oxide film, latchup, which has been conventionally problematic, will not occur.
Because of the above features, high speed operation without latchup can be expected by forming a gate array on an SOI substrate.
In an MOS field effect transistor fabricated on the conventional SOI substrate, the breakdown voltage between source and drain is lowered as compared to an MOS field effect transistor fabricated on the bulk silicon substrate, because of the substrate floating effect of an SOI layer serving as a channel. Referring to.
FIGS. 83 and 84
, described is how the breakdown voltage between source and drain is lowered because of the substrate floating effect.
FIG. 83
shows the Id-Vd characteristics of an MOS field effect transistor fabricated on a bulk silicon substrate, and
FIG. 84
shows the Id-Vd characteristics of an MOS field effect transistor fabricated on an SOI substrate.
Referring to these figures, in the MOS field effect transistor fabricated on the bulk silicon substrate, the breakdown voltage is 5V or more. On the other hand, in the MOS field effect transistor fabricated on the SOI substrate, the breakdown voltage is only approximately 2V.
Description will now be given of the substrate floating effect with reference to
FIGS. 85 and 86
. A hole
338
generated by impact ionization in a depletion layer in the vicinity of a drain region
334
is stored in a lower portion of a channel region
332
in the vicinity of a source region
330
. Holes
338
are sequentially accumulated in the lower portion of channel region
332
, thereby increasing the potential of an SOI layer to induce injection of an electron
336
from source region
330
. The injected electron
336
reaches the vicinity of drain region
334
to generate new hole
338
. As described above, a so-called feed forward loop formed by injection of electron
336
and generation of hole
338
causes the breakdown voltage between source and drain to decrease.
In order to prevent the substrate floating effect, several methods are being studied. The most reliable one is a method of preventing storage of holes
338
by fixing the potential of a channel region
344
, with reference to FIG.
87
. In the case of an n type MOS field effect transistor, for example, storage of holes
338
can be prevented by fixing the potential of the channel region to ground potential. Similarly, in the case of a p type MOS field effect transistor, storage of holes
338
can be prevented by fixing the potential of the channel region to power supply potential. In order to fix the potential of channel region
332
, the SOI layer under gate electrode
304
is drawn out, and a region
350
for providing a body contact
352
is formed. As a result, storage of holes
338
can be prevented. However, this method necessitates an additional region
350
for forming a body contact, which hampers high integration of a semiconductor device.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a semiconductor device preventing reduction of a breakdown voltage between source and drain, which has been a problem to an MOS field effect transistor formed on a conventional SOI substrate, and a method of manufacturing the same.
Another object of the present invention is to
Inoue Yasuo
Iwamatsu Toshiaki
Nishimura Tadashi
Yamaguchi Yasuo
Abraham Fetsum
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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