Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-04-10
2002-11-26
Munson, Gene M. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S190000, C257S192000, C257S196000, C257S412000, C257S616000
Reexamination Certificate
active
06486520
ABSTRACT:
FIELD OF THE INVENTION
This invention generally pertains to the integration of dielectrics with integrated circuits. and more particularly to reaction barriers between large-permittivity dielectrics and an underlyin semiconductor layer.
BACKGROUND OF THE INVENTION
Semiconductors are widely used in integrated circuits for electronic devices such as computers and televisions. These integrated circuits typically combine many transistors on a single crystal silicon chip to perform complex functions and store data. Semiconductor and electronics manufacturers, as well as end users, desire integrated circuits that can accomplish more functions in less time in a smaller package while consuming less power.
Generally, an arrangement of layers with an oxide between a conducting layer and a semiconductor is usable as a portion of many of the structures used in semiconductor circuitry, such as capacitors, MOS transistors, pixels for light detecting arrays, and electrooptic applications, SiO
2
is the primary oxide used in semiconductors today. The integration of non-SiO
2
based oxides directly or indirectly on Si is difficult because of the strong reactivity of Si with oxygen. The deposition of non-SiO
2
oxides on Si has generally resulted in the formation of a SiO
2
or silicate layer at the Si // oxide interface. This layer is generally amorphous and has a low dielectric constant. These properties degrade the usefulness of non-SiO
2
based oxides with Si.
High-dielectric constant (HDC) oxides (e.g. a ferroelectric oxide) can have a large dielectric constant, a large spontaneous polarization, and large electrooptic properties. Ferroelectrics with a large dielectric constant can be used to form high density capacitors but can not deposited directly on Si because of the reaction of Si to form a low dielectric constant layer. Such capacitor dielectrics have been deposited on “inert” metals such as Pt, but even Pt or Pd must be separated from the Si with one or more conductive buffer layers. Putting the high dielectric material on a conductive layer (which is either directly on the semiconductor or on an insulating layer which is on the semiconductor) has not solved the problem. Of the conductor or semiconductor materials previously suggested for use next to high dielectric materials in semiconductor circuitry, none of these materials provides for the epitaxial growth of high dielectric materials on a conductor or semiconductor. Further, the prior art materials generally either form a silicide which allows the diffusion of silicon into the high dielectric materials, or react with silicon or react with the high dielectric oxide to form low dielectric constant insulators.
The large spontaneous polarization of ferroelectrics when integrated directly on a semiconductor can also be used to form a non-volatile, non-destructive readout, field effect memory. This has been successfully done with non-oxide ferroelectrics such as (Ba,Mg)F
2
but not so successfully with oxide ferroelectrics because the formation of the low dielectric constant SiO
2
layer acts to reduce the field within the oxide. The oxide can also either poison the Si device or create so many interface traps that the device will not operate properly. Ferroelectrics also have interesting electrooptic applications where epitaxial films are preferred in order to reduce loss due to scattering from grain boundaries and to align the oxide in order to maximize its anisotropic properties. The epitaxial growth on Si or GaAs substrates has previously been accomplished by first growing a very stable oxide or fluoride on the Si or GaAs as a buffer layer prior to growing another type of oxide. The integration of oxides on GaAs is even harder than Si because the GaAs is unstable in O
2
at the normal growth temperatures of 450° C.-700° C.
In another integrated circuit area, prior art devices use SiO
2
based films with thicknesses of 5 nm or more for the gate dielectric in conventional MOS (metal-oxide-semiconductor) circuits. For future small geometry devices the thickness of the gate dielectric is projected to be less than 4 nm. then less than 3 nm, and eventually less than 2 nm. One reason for this is that the current drive in a MOS transistor is directly proportional to the gate capacitance. Because capacitance scales inversely with thickness, higher current drive requires continual reductions in the thickness for conventional dielectrics. SiO
2
gate dielectrics in this thickness region. however. pose considerable challenges, such as breakdown and tunneling problems, as well as manufacturing process control problems. For example, direct tunneling through the SiO
2
may occur, although the effect of tunneling current on device performance may not preclude operation. Because the tunnel current depends exponentially on the dielectric thickness, small variations in process control may result in large variations in the tunnel current, possibly leading to localized reliability problems. In addition, SiO
2
at these reduced thicknesses provides very little barrier to diffusion. Thus the diffusion of boron from doped polysilicon gates, for example, would result in an increasingly difficult problem as geometries shrink.
SUMMARY OF THE INVENTION
A Ge buffer layer directly or indirectly on Si oxidizes much less readily than Si, and can be used to prevent or minimize the formation of a low dielectric constant layer. An epitaxial Ge layer on Si provides a good buffer layer which is compatible with Si and also many oxides. Unlike other buffer layers, Ge is a semiconductor (it can also be doped to provide a reasonably highly conductive layer) and is compatible with Si process technology. The epitaxial growth of Ge on top of a large-permittivity oxide is also much easier than Si which makes it possible to form three dimensional epitaxial structures. The Ge buffer layer can be epitaxially grown on the Si substrate allowing the large-permittivity oxide to be epitaxially grown on the Ge and hence epitaxially aligned to the Si substrate. The epitaxial Ge layer allows ferroelectrics to be directly grown on Si wafers to form non-volatile non-destructive read out memory cells. The Ge buffer layer will also increase the capacitance of large-permittivity oxide films compared to films grown directly on Si. A Ge buffer layer on the Si or GaAs substrate allows many more oxides to be epitaxially grown on it because of the much smaller chemical reactivity of Ge with oxygen compared to Si or GaAs with oxygen.
Generally the prior art conductive materials suggested for interfacing with large-permittivity oxides in semiconductor circuitry either have reacted with the large-permittivity oxides or with the semiconductor and/or have not provided a diffusion barrier between the large-permittivity oxides and semiconductor material. As noted, the integration of oxides on GaAs is even harder than on Si because GaAs is unstable in O
2
at the normal growth temperatures of high-dielectric constant oxides (450 C.-700° C.), and at the growth temperatures of some moderate-dielectric constant oxides. An epitaxial Ge buffer layer solves this problem and simplifies the integration of large-pennittivity oxides on GaAs for the same applications as listed above.
A structure for, and method of forming, a memory cell in an integrated circuit is disclosed. This is a method for fabricating a structure useful in semiconductor circuitry comprising growing a germanium layer on a non-germanium semiconductor substrate, and depositing a high-dielectric constant oxide on the germanium layer. Preferably, the germanium layer is epitaxially grown on the semiconductor substrate. This is also a structure useful in semiconductor circuitry comprising a semiconductor substrate, a germanium layer on the semiconductor substrate, and a high-dielectric constant oxide on the germanium layer. Preferably the germanium layer is single-crystal. Preferably, the substrate is silicon and the germanium layer is less than about 1 nm thick, or the substrate is gallium arsenide (in which case the thickness of the germanium l
Okuno Yasutoshi
Summerfelt Scott R.
Brady III Wade James
Denker David
Munson Gene M.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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