Electrical computers and digital processing systems: support – Digital data processing system initialization or configuration
Reexamination Certificate
1999-03-09
2002-06-04
Heckler, Thomas M. (Department: 2185)
Electrical computers and digital processing systems: support
Digital data processing system initialization or configuration
Reexamination Certificate
active
06401198
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to an arrangement for and method of operating a computer system including a host computer having system Random Access Memory (RAM) and using a Basic Input/Output System (BIOS) to operate the host computer. More particularly the arrangement and method of the invention stores at least a portion of the BIOS used to operate the system within the mass memory storage of a mass memory storage peripheral computer device rather than in Read Only Memory (ROM). The BIOS stored in the mass storage media may be expansion BIOS associated with a particular peripheral computer device and/or system BIOS associated with the host computer. The ROM refers to either system ROM provided by the host computer or peripheral ROM provided by a peripheral device (either on a card or on the device itself).
BACKGROUND OF THE INVENTION
The computer industry is continuously evolving, providing faster processors, larger memory capacities, and a variety of peripheral devices which may be interconnected with a host computer. Due to these increasing speeds and capacities, one of the developments in the industry is a peripheral bus implementation known as Peripheral Components Interface (PCI). This peripheral bus has been developed to provide an expansion mechanism between the host computer and peripheral computer devices or expansion boards.
The PCI peripheral bus is designed to be both processor and computer system architecture independent with the PCI electrical, protocol, and hardware interface requirements remaining the same regardless of the CPU or host system computer architecture being used. This allows the same peripheral computer device to be connected to a variety of different host systems without requiring different versions of the device for each type of host system with which the device is intended to be used. Because the PCI bus is independent of the processor and the computer architecture, each host system is required to provide a mechanism to map host I/O and memory space to the addressing mechanism used on the PCI bus. This is also true of the expansion ROM memory space of a peripheral computer device, which typically includes initializing information and operating information such as code and data for that peripheral computer device. Therefore, relocatable expansion ROM location addresses are allowed on a PCI device. This is not the case for earlier bus architectures such as the Industry Standard Architecture (ISA) Bus.
As shown in
FIG. 1
, which illustrates one example of a typical PCI-based computer system designated by reference numeral
10
, system
10
includes a host computer
12
having a system BIOS
13
for operating host computer
12
and having system RAM memory
14
associate with host computer
12
. System BIOS
13
is stored in system ROM
15
within host computer
12
. A PCI peripheral bus
16
is connected to host computer
12
and system RAM
14
using a host bridge
17
. The system also includes a peripheral computer device
18
, for example a hard disk drive, which is connected to the PCI bus such that the host computer may communicate with the peripheral computer device using the PCI bus. Device
18
includes ROM
20
which contains any expansion BIOS
22
required in the host system in order to initialize and/or operate peripheral computer device
18
. In a system using the PCI bus, the host system BIOS and/or operating system must provide a configuration manager that recognizes individual PCI devices, allocates resources, and enables those devices. It is the responsibility of the configuration manager to copy any expansion BIOS of the peripheral device into the host computer's RAM and then execute any initialization routine provided within the expansion BIOS to provide proper peripheral device initialization.
Referring to
FIG. 2A
, which diagrammatically illustrates the expansion BIOS
22
contained in ROM
20
, the PCI specification allows for multiple code images, for example
24
a
-
24
d
, to be stored within the expansion BIOS
22
with each code image providing the appropriate information for a particular computer architecture. In this example, code image
24
a
might correspond to an Intel® based system, code image
24
b
might correspond to a Power PC® based system, and so on. These multiple code images
24
a
-
24
d
increase the amount of information which is included in the expansion BIOS thereby increasing the amount of ROM required to store the expansion BIOS
22
. As shown in
FIG. 2B
, code image
24
a
, and each of the other images, includes a header region
26
. Depending on the requirements of device
18
to which the expansion BIOS
22
corresponds, each image may also include a data structure region
28
, runtime code
30
, initialization code
32
, and a check sum
34
. Referring to
FIG. 2C
, the PCI specification also requires that each PCI device includes a configuration space memory
35
which is 256 bytes in size and which conforms to the PCI format illustrated. The information provided by configuration space
35
includes a device ID register
36
containing the device identification and a configuration register
38
containing a requested amount of memory space. The configuration register
38
specifies the amount of memory space required within the host computer memory to map the expansion BIOS
22
associated with peripheral computer device
18
.
As will be described in more detail immediately hereinafter, once expansion BIOS
22
has been copied into host system RAM
14
, the initialization code
32
from the proper code image, for example code image
24
a
, is run. This initializes device
18
and provides the proper hooks into the system for operating device
18
using runtime code
30
from the proper code image, in this case, image
24
a
, as contrasted with image
24
b, c
, or
d
. Once the initialization code has been run, control is returned to the host system and only the code required for operating device
18
is left in host system RAM
14
where it remains throughout the operation of the system. The excess information of the proper code image
24
a
being only necessary for initialization of device
18
is no longer necessary. Therefore, the memory used to store this excess information is made available to be used again by host computer
12
, thereby reducing the usage of RAM
14
to store the necessary portions of expansion BIOS
22
.
Referring now to
FIG. 3
, a typical sequence for obtaining expansion BIOS from a PCI peripheral device and storing it within, system RAM will be described in detail using the example of system
10
described above. After computer system
10
is turned on, indicated in block
40
of
FIG. 3
, the processor of host computer
12
starts running system code typically called Power-On-Self-Test (POST) as indicated by block
42
. The POST code performs unrelated system configurations (block
44
) and then starts the configuration of the PCI bus add-on peripheral devices by checking for the presence of peripheral devices, such as peripheral device
18
, as indicated by decision box
46
. Once the POST code finds peripheral device
18
and as respectively indicated in blocks
48
,
50
, and
52
of
FIG. 3
, the POST code starts the configuration of device
18
, allocates host I/O and RAM memory space as requested by device
18
, and configures interrupt and allocates IRQs on host computer
12
as requested by device
18
. At this point, the POST code determines if device
18
has an expansion BIOS that needs to be loaded and configured as indicated by decision block
54
. If there is no expansion BIOS, as indicated by clock
56
, the POST code goes on to the next peripheral device. If all the devices are configured, the POST code goes on to boot the operating system as shown in block
58
. If, however, there is an expansion BIOS to be loaded from the device, as is the case for device
18
, the expansion BIOS is loaded and configured as indicated by block
60
. Once this loading of the expansion BIOS for device
18
is completed, the sequen
Bruner Curtis H.
Harmer Tracy D.
Brady W. James
Heckler Thomas M.
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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