Two step plasma etch using variable electrode spacing

Details Two step plasma etch using variable electrode spacing Two step plasma etch using variable electrode spacing

2000-08-16

2002-11-19

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S706000, C438S714000, C438S716000, C438S723000

Reexamination Certificate

active

06482744

ABSTRACT:

FILED OF THE INVENTION
The present invention relates to etching, and more specifically, to a method of etching using variable electrode spacing.
BACKGROUND OF THE INVENTION
Etching in semiconductor processing has inherent limitations. An ideal anisotropic etch leaves vertical walls in the resist and metal layers. However, because the etching chemical dissolves the top of the wall for a longer time than the bottom, the resulting hole is wider at the top than at the bottom. Hence, the etch is somewhat isotropic.
Dry etching processes, such as reactive ion etching, have decreased this problem. Dry etch techniques rely in part on material from the masking layer (usually photoresist) to achieve anisotropic profiles. This has the undesirable side effect of making the etch anisotropically sensitive to masking pattern density.
Another difficulty with prior etching techniques is that the etching varies over the surface of the wafer. In other words, certain portions of the wafer are over etched, while other portions of the wafer are under etched. The above are merely examples of etching limitations.
The etching process is performed in an etching tool, such as the tools manufactured by Tokyo Electron Ltd. (TEL) of Tokyo, Japan. TEL manufactures a dipole ring magnetron (DRM) etching tool called the Unity DRM. This tool is described in U.S. Pat. No. 6,014,943 to Arami et al. In the Unity DRM etching tool, a semiconductor wafer is subjected to a plasma atmosphere which is generated by introducing a process gas into a process vessel and converting the process gas into a plasma-state gas.
In recent years, the degree of integration of semiconductor devices has been increased and critical dimensions have decreased. One of the more difficult etching problems is evenly etching contact vias for connection to a bitline of a DRAM memory array, particularly over the entire surface of the wafer.


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patent: 6199561 (2001-03-01), Mitsuhashi
patent: 6235640 (2001-05-01), Ebel et al.

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