Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-06-01
2002-12-10
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S298000, C257S329000, C257S401000, C257S305000, C257S303000, C257S369000, C257S279000
Reexamination Certificate
active
06492674
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device in which a conductive plug embedded in a contact hole (corresponding to an interconnection hole) and an interconnect utilizing a trench are formed simultaneously, as well as to a semiconductor device manufactured by the method.
2. Background Art
With tendency toward a rapid reduction in size of a semiconductor element, minute contacts and interconnections are ever demanded. In a conventional semiconductor device with low integration level, contact holes or interconnection holes are formed in a dielectric film to establish electrical contact between active regions. Further, a wafer is etched after deposition of material for interconnections.
In recent years, a mixed-manufacturing process has become dominant for manufacturing a memory device, typified by dynamic random access memory (DRAM), and a logic device on a single wafer. In such a DRAM, a thickness of an interlayer insulating film is increased to fabricate an internal capacitor, so that a deep contact hole or an interconnection hole must be formed. Thus, difficulty is imposed in the process of forming contacts and interconnections.
FIG. 20
is a cross-sectional view for explaining a principal structure of a conventional semiconductor device. In a conventional semiconductor device
100
C in which a DRAM and a logic device are formed in a same device, a thick interlayer oxide film is needed for manufacturing a capacitor. However, contact holes or interconnection holes could not be formed in the thick interlayer oxide film in a single process. For instance, as shown in
FIG. 20
, a first conductive plug
40
is connected to a second conductive plug
6
, and the plug
6
is connected to a gate electrode
5
of a MOSFET which is isolated by an isolation oxide film
2
provided in a semiconductor substrate or a silicon substrate
1
. Thus, a two-layer configuration of the plug
6
and the plug
40
is needed in the manufacturing process.
A lower interconnecting layer
50
provided between the first conductive plug
40
and the second conductive plugs
6
establishes local electrical connection. When the same material is used for the second conductive plugs
6
and the lower interconnecting layer
50
, a certain minimum distance must be ensured between adjacent lower interconnecting layers
50
, resulting in deterioration of the packing density of the integrated circuit. In order to avoid such deterioration in packing density, the lower interconnecting layer
50
must be formed from material differing from that of the second conductive plugs
6
.
An upper interconnecting layer
51
establishes local electrical connection, as does the lower interconnecting layer
50
. When the same material is used for the first conductive plug
40
and the upper interconnecting layer
51
, a certain minimum distance must be ensured between the adjacent upper interconnecting layers
51
, thus deteriorating the packing density of the integrated circuit. In order to avoid such deterioration in packing density, the upper interconnecting layer
51
must be formed from material differing from that of the first conductive plug
40
.
SUMMARY OF THE INVENTION
The present invention has been conceived to solve the problem as set forth and is aimed at providing a method of manufacturing a semiconductor device which enables facilitated formation of a plug and an interconnection simultaneously in a minute pattern when forming a conductive plug in a contact hole and forming an interconnection in a trench. Thus, a high-integration semiconductor device is manufactured.
According to one aspect of the present invention, a semiconductor device comprises a semiconductor substrate, a first semiconductor element having a first gate electrode and a pair of active regions by the gate electrode, an a second semiconductor element having a second gate electrode and a pair of active regions by the gate electrode. An isolating layer is formed on the semiconductor substrate to isolate the first and second semiconductor elements. An interlayer insulating film is formed on the semiconductor substrate. A first conductive plug is formed in the interlayer insulation film and on the isolating layer, and the first conductive plug electrically connects one of the active regions of the first semiconductor element and one of the active regions of the second semiconductor element.
According to another aspect of the present invention, a semiconductor device comprises a semiconductor substrate, a first semiconductor element having a first gate electrode and a pair of active regions by the gate electrode, and a second semiconductor element having a second gate electrode and a pair of active regions by the gate electrode. An isolating layer is formed on the semiconductor substrate to isolate the first and second semiconductor elements. A conductive line is formed on said isolating layer. An interlayer insulating film is formed on the semiconductor substrate. Further, a first conductive plug is formed in the interlayer insulating film and on the isolating layer, and the first conductive plug electrically connects said conductive line and at least one of the active regions of the first semiconductor element or the second semiconductor element.
Other and further objects, features and advantages of the present invention will appear more fully from the following description.
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patent: 5624863 (1997-04-01), Helm et al.
patent: 5807779 (1998-09-01), Liaw
patent: 5970335 (1999-10-01), Helm et al.
patent: 6069038 (2000-05-01), Hashimoto et al.
patent: 6118158 (2000-09-01), Kim
patent: 6300229 (2001-10-01), Tanaka et al.
patent: 10-50950 (1998-02-01), None
patent: 11-186386 (1999-07-01), None
McDermott & Will & Emery
Yevsikov V.
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