Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-08-13
2002-12-31
Quach, T. N. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S641000, C257S760000, C257S774000
Reexamination Certificate
active
06501141
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a method for fabricating a semiconductor device and more particularly, relates to a method of fabricating a self-aligned contact window with silicon nitride sidewall spacers. The present invention can be utilized in a photolithographic process and in an etching process to improve the isolation of a metal contact.
BACKGROUND OF THE INVENTION
Semiconductor devices manufactured in and on a semiconductor substrate are very closely spaced. The alignment, lithography technologies are more important than ever due to the fact that the packing density is continuously increased. In the prior art, there is a poor silicon oxide thickness control of LDD spacer and isolation layer formed by a plasma etch process. The tolerance for a self-aligning process for a contact is degraded, since the size of a contact window is reduced by the scaling down in dimensions of the feature formed on a wafer. In the self-aligned contact forming process, a gate electrode is generally exposed when the dielectric layer is etched to form the contact window. The exposed gate electrode may cause a gate leakage problem. The problem may be caused by the cap layers and the spacers been etched during the above mentioned etching steps in forming the contact window.
U.S. Pat. No. 5,208,472 issued to Su et al, cites the use of dual spacers alongside a polysilicon gate electrode. A first spacer is used to define the source/drain implantation and a second spacer to define silicide contact further away from the gate electrode, thereby reducing gate-to-source/drain bridging. The spacers may be formed of silicon oxide or silicon nitride. U.S. Pat. No. 4,988,643 issued to Tsou, shows the use of a silicon nitride cap over a polysilicon gate to prevent oxidation of the gate electrode.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating an integrated circuit device having self-aligned contact window for overcoming the problem of photolithographic techniques.
It is another object of the present invention to a method for fabricating self-aligned contact window with silicon nitride sidewall spacers that have improved isolation characteristics. A gate oxide layer, a polysilicon layer, a metal silicide layer, a first silicon dioxide layer, a silicon nitride cap layer, and a second silicon oxide layer are subsequently deposited on a substrate. The gate oxide layer, the polysilicon layer, the metal silicide layer, the first silicon dioxide layer, the silicon nitride cap layer, and the second silicon oxide layer are etched to form the gate structure with a thin unetched polysilicon left on the gate oxide. Partially wet etch the first silicon oxide layer and the second silicon oxide layer on the gate structure by an etchant that has high selectivity toward silicon oxide. The width of the first silicon oxide is smaller than the width of the silicon nitride cap layer. Remove the thin unetched polysilicon on the gate oxide layer. Next, a second silicon nitride layer is deposited on the second silicon oxide layer. Then, an etching technique is used to form the sidewall spacers. The sidewall spacers composed of silicon nitride layer are used as etching barriers to prevent the polysilicon gate from being exposed during the formation of a contact window using the etch step. A dielectric layer is formed on the spacers and the second silicon dioxide layer. An etching process is used to etch the dielectric layer to create a contact hole that has improved isolation.
REFERENCES:
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patent: 5751048 (1998-05-01), Lee et al.
patent: 6278189 (2001-08-01), Jeng et al.
patent: 6355547 (2002-03-01), Lee et al.
patent: 2001/0055867 (2001-12-01), Lee
patent: 2002/0014657 (2002-02-01), Ohiwa et al.
Quach T. N.
Taiwan Semiconductor Manufacturing Company Ltd
Tung & Associates
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