Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-01-09
2002-10-29
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S309000
Reexamination Certificate
active
06472704
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having a contact hole and a method of manufacturing the same.
2. Description of the Background Art
A DRAM (Dynamic Random Access Memory) is conventionally well known as a semiconductor memory which is a type of semiconductor devices.
FIG. 35
is a cross sectional view showing a conventional DRAM. Referring to
FIG. 35
, a cross sectional structure of the conventional DRAM will be described first.
In a memory cell portion of the conventional DRAM, an isolation region
102
is provided in a prescribed region at the main surface of a silicon substrate
101
. Source/drain regions
106
a
,
106
b
and
106
c
are formed in an active region surrounded by isolation region
102
. On a channel region between source/drain regions
106
a
,
106
b
, a gate electrode
104
a
is formed with a gate oxide film
103
therebetween. Gate electrodes
104
b
and
104
c
are formed spaced apart from gate electrode
104
a
by a prescribed distance. A TEOS oxide film
105
is formed to cover the top surfaces of gate electrodes
104
a
to
104
c
. A sidewall oxide film
107
is formed to be in contact with side surfaces of gate electrodes
104
a
to
104
c
and of TEOS oxide film
105
.
A silicon nitride film
108
is formed to cover TEOS oxide film
105
, sidewall oxide film
107
, and source/drain regions
106
a
to
106
c
. An interlayer insulating film
109
is formed on silicon nitride film
108
. A bit line contact hole
160
is formed in the region of silicon nitride film
108
and interlayer insulating film
109
located on source/drain region
106
b
. A bit line
110
a
is formed to be electrically connected to source/drain region
106
b
through bit line contact hole
160
and to extend on the top surface of interlayer insulating film
109
.
An interlayer insulating film
111
is formed on bit line
110
a
and interlayer insulating film
109
. A capacitor contact hole
161
is formed in the region of silicon nitride film
108
and interlayer insulating films
109
,
111
located on source/drain region
106
a
. A doped polycrystalline silicon film
112
is formed to be electrically connected to source/drain region
106
a
through capacitor contact hole
161
and to extend on the top surface of interlayer insulating film
111
. Doped polycrystalline silicon film
112
includes a vertical part
112
a
electrically connected to source/drain region
106
a
and filling contact hole
161
, and a horizontal part
112
b
formed integrally with this vertical part
112
a
and serving as a capacitor lower electrode.
A sidewall
113
of a doped polycrystalline silicon film is formed to come into contact with both side end surfaces of horizontal part
112
b
and to extend vertically. Sidewall
113
also serves as the capacitor lower electrode. To cover the top surface of horizontal part
112
b
and the surface of sidewall
113
, a capacitor upper electrode
115
is formed thereon with a capacitor dielectric film
114
therebetween. Capacitor upper electrode
115
includes a doped polycrystalline silicon film. Capacitor lower electrode
112
b
,
113
, capacitor dielectric film
114
, and capacitor upper electrode
115
constitute a capacitor. An interlayer insulating film
116
is formed to cover the capacitor. On the top surface of interlayer insulating film
116
, metal interconnections
118
are formed spaced apart by a prescribed distance.
On the other hand, in a peripheral circuitry portion, source/drain regions
106
d
and
106
e
are formed spaced apart by a prescribed distance at the main surface of silicon substrate
101
. On a channel region between source/drain regions
106
d
,
106
e
, a gate electrode
104
e
is formed with gate oxide film
103
therebetween. On the region separated from gate electrode
104
e
by source/drain region
106
d
, a gate electrode
104
d
is formed with gate oxide film
103
therebetween. TEOS oxide film
105
is formed on the top surfaces of gate electrodes
104
d
and
104
e
. Sidewall oxide film
107
is formed to come into contact with the side surfaces of gate electrodes
104
d
and
104
e
and of TEOS oxide film
105
.
Interlayer insulating film
109
is formed to cover source/drain regions
106
d
,
106
e
, sidewall oxide film
107
, and TEOS oxide film
105
. A contact hole is formed in the region of interlayer insulating film
109
located on source/drain region
106
d
and in the region of interlayer insulating film
109
located on gate electrode
104
e
. Inside these contact holes, an interconnection layer
110
b
is formed to be electrically connected to source/drain region
106
d
and gate electrode
104
e
. Here, interconnection layer
110
b
may be connected to either one of source/drain region
106
d
or gate electrode
104
e
. Interlayer insulating film
111
is formed to cover interconnection layer
110
b
, and interlayer insulating film
116
is formed to cover this interlayer insulating film
111
. A contact hole is formed in the region of interlayer insulating films
111
and
116
located on a side end of interconnection layer
110
b
. A metal interconnection
117
is formed to be electrically connected to interconnection layer
110
b
through the contact hole and to extend along interlayer insulating film
116
.
FIG. 36
shows a top plan layout of the entire memory cell portion of the above described conventional DRAM. Referring to
FIG. 36
, in the memory cell portion of the conventional DRAM, gate electrodes
104
a
to
104
c
are formed to extend in parallel, spaced apart by a prescribed distance. In a direction perpendicular to gate electrodes
104
a
to
104
c
, bit lines
110
a
are formed to extend almost in parallel, spaced apart by a prescribed distance. Bit line
110
a
is connected to source/drain region
106
b
in an active region
170
through bit line contact hole
160
. Doped polycrystalline silicon film
112
serving as the capacitor lower electrode is connected to source/drain region
106
a
in active region
170
through capacitor contact hole
161
.
FIGS. 37
to
53
are cross sectional views illustrating a manufacturing process of the conventional DRAM shown in FIG.
35
. Referring to
FIGS. 37
to
53
, the manufacturing process of the conventional DRAM will be described below.
First, isolation region
102
is formed at the main surface of silicon substrate
101
in the memory cell portion, as shown in FIG.
37
. On the main surface of silicon substrate
101
, gate oxide films
103
are formed spaced apart by a prescribed distance. Respective gate electrodes
104
a
,
104
b
and
104
c
are formed on gate oxide films
103
. In the peripheral circuitry portion as well, gate electrodes
104
d
and
104
e
are respectively formed on gate oxide films
103
. By ion-implanting an impurity into silicon substrate
101
while using gate electrodes
104
a
to
104
e
as a mask, source/drain regions
106
a
to
106
e
are formed.
TEOS oxide film
105
is formed on the top surfaces of gate electrodes
104
a
to
104
e
. Sidewall oxide film
107
is formed to come into contact with side surfaces of gate electrodes
104
a
to
104
e
and of TEOS oxide film
105
. By ion-implanting an impurity into source/drain regions
106
d
and
106
e
again, while using sidewall oxide film
107
in the peripheral circuitry portion as a mask, source/drain regions
106
d
and
106
e
of the LDD structure are completed.
Then, silicon nitride film
108
as an etching stopper layer is formed to cover the entire memory cell portion as shown in FIG.
38
. Interlayer insulating film
109
including a silicon oxide film is formed to cover silicon nitride film
108
and the entire peripheral circuitry portion.
Thereafter, contact holes
109
a
to
109
c
as shown in
FIG. 39
are formed by photolithography and dry etching. In etching for forming contact hole
109
a
in the memory cell portion, silicon nitride film
108
serves as an etching stopper lay
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Thomas Tom
Tran Thien F
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