Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-03-24
2002-10-22
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S360000, C257S363000, C257S409000, C257S484000
Reexamination Certificate
active
06469354
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a semiconductor device having a protective circuit, and more particularly to a structure of a protective transistor capable of protecting the internal circuit of the semiconductor device against an electrostatic breakdown.
(b) Description of the Related Art
In general, when electrostatic charge enters a semiconductor device during the course of a fabrication or inspection process, or during a stage of mounting the semiconductor device onto electronic equipment, the internal circuit of the semiconductor device is prone to breaking. Therefore, a protective transistor is generally provided at an input/output port of a semiconductor device through which the internal circuit is connected to an external circuit.
FIGS. 1A and 1B
show two of a plurality of input/output circuit sections of a typical semiconductor device. These input/output circuit sections are provided at peripheral portions of a chip of the semiconductor device so as to surround the internal circuit. Each of the input/output circuit sections is composed of paired nMOSFETs
31
and pMOSFETs
32
. As shown in
FIGS. 1A and 1B
, by means of interconnects overlying the substrate, the input/output circuit section is fabricated selectively as a protective circuit or an output buffer. Alternatively, a portion of the input/output circuit section is fabricated as a protective circuit and the remaining portion is formed as an output buffer. The structure of such a transistor will be described with reference to the nMOSFET
31
. In the present example, each nMOSFET
31
includes four protective transistors. The drain region
14
n
are connected to a pair of gate electrodes
15
n
in common. Similarly, the source regions
16
n
formed are connected to a pair of gate electrodes
15
n
in common. A via hole
13
provides connection between an overlying interconnect layer and an underlying drain region
14
n
or source region
16
n
. Each guard ring
18
n
is formed to surround the drain regions
14
n
and the source regions
16
n
and is connected to the ground line GND (in the case of nMOSFET
31
). The guard ring
18
n
surrounding the transistors fixes the potential of the well or the substrate. In the case of nMOSFET
31
, the drain regions
14
n
and the source regions
16
n
are implemented by an N+ diffused layer, the guard ring
18
n
is implemented by a P+ diffused layer, and the well
11
n
is of a P-conductivity type. By contrast, in the case of pMOSFET
32
, the drain regions
14
p
and the source regions
16
p
are formed of a P+ diffused layer, the guard ring
18
p
is formed of an N+ diffused layer, and the well
11
p
is of an N-conductivity type. The guard ring
18
p
is connected to a power supply line VDD.
FIG. 1A
is a top plan view of the input/output circuit section in the case of an input protective circuit, and
FIG. 2A
is an equivalent circuit diagram of the input/output circuit section of FIG.
1
A. The drain regions
14
n
of the nMOSFET
31
and the drain regions
14
p
of the pMOSFET
32
are connected together, via an overlying interconnect
14
a
, to a pad
22
and an unillustrated input buffer of the internal circuit. The source regions
16
n
of the Cap nMOSFET
31
are connected, via the via holes
13
, to the gate electrodes
15
n
as well as to the ground line GND. The source regions
16
p
of the pMOSFET
32
are connected, via the via holes
13
, to the gate electrodes
15
p
as well as to the power supply line VDD. Through these connections, the input/output circuit section functions as an input protective circuit.
FIG. 1B
is a top plan view of the input/output circuit section in the case of an output buffer, and
FIG. 2B
is an equivalent circuit diagram of the input/output circuit section of FIG.
1
B. The drain regions
14
n
of the nMOSFET
31
and the drain regions
14
p
of the pMOSFET
32
are connected to another pad
22
via another interconnect
14
a
. The gate electrodes
15
n
and
15
p
are connected to an output of an unillustrated output pre-buffer of the internal circuit. When the output pre-buffer has a pair of complementary output lines, the gate electrodes
15
n
and
15
p
are connected to the output pre-buffer via a pair of signal lines. When the output pre-buffer has a single output, the gate electrodes
15
n
and
15
p
are connected to the output pre-buffer via a single signal line (not illustrated). The source regions
16
n
of the nMOSFET
31
are connected to the ground line GND via the via holes
13
, and the source regions
16
p
of the pMOSFET
32
are connected to the power supply line VDD via the via holes
13
. Through these connections, the input/output circuit section functions as an inverter and as a protective circuit.
FIG. 2C
is an equivalent circuit diagram of an input/output circuit section, a part of which is formed as an input protective circuit, and the remaining portion of which is formed as an output buffer. In this case, among four transistors of each of the pMOSFET
32
and the nMOSFET
31
, two transistors are used in order to form the input protective circuit, and the remaining transistors are used in order to form the output buffer. The connections for formation of the input protective circuit and the connections for formation of the output buffer are performed similarly to the case as described above. That is, the drain regions
14
n
of the nMOSFET
31
and the drain regions
14
p
of the pMOSFET
32
are connected together to the pad
22
via the interconnection layer
14
a
. The source regions
16
n
of the nMOSFET
31
constituting the input protective circuit are connected, via the via holes
13
, to the gate electrodes
15
n
thereof as well as to the ground line GND. The source regions
16
p
of the pMOSFET
32
are connected, via the via holes
13
, to the gate electrodes
15
p
thereof as well as to the power supply line VDD. The gate electrodes
15
n
and
15
p
of the transistors constituting the output buffer are connected to an unillustrated output pre-buffer of the internal circuit. The source regions
16
n
of the nMOSFET
31
are connected to the ground line GND via the via holes
13
, and the source regions
16
p
of the pMOSFET
32
are connected to the power supply line VDD via the via holes
13
. Through these connections, the input/output circuit section functions as an input protective circuit and as an output buffer.
Next, the operation of the input protective circuit formed by the input/output circuit section will be described with reference to
FIGS. 3A and 3B
.
FIG. 3A
is a cross section of the guard ring
18
n
of the nMOSFET
31
and a protective transistor adjacent thereto.
FIG. 3B
is a graph showing the input/output characteristics of the protective transistor. In
FIG. 3A
, since the drain
14
n
and the source
16
n
are formed of an N+ diffused layer, and a portion of the P-well
11
located beneath the gate
15
n
is of a P-conductivity type, an NPN parasitic transistor
12
is formed beneath the gate
15
n
. Specifically, the drain
14
n
corresponds to the collector
14
c
, the P-well
11
corresponds to the base
11
c
, and the source
16
n
corresponds to the emitter
16
c
of the parasitic transistor
12
. The collector
14
c
is connected to the pad
22
, and the emitter
16
c
is connected to the ground together with the guard ring
18
n
. A parasitic resistor
17
is formed between the base
11
c
and the guard ring
18
n
. In an ordinary state, since no voltage is applied to the base
11
c
, the parasitic transistor
12
is in an off state.
Next, the principle of the protective transistor will be described with reference to FIG.
3
B. The abscissa represents the emitter-to-collector voltage (source-to-drain voltage), and the ordinate represents the collector current. Assuming that, due to electrostatic charge, positive surge voltage enters from the pad
22
, a strong electric field is generated between the collector
14
c
and the emitter
16
c
, with the result that breakdown star
Foley & Lardner
Loke Steven
NEC Corporation
Vu Hung Kim
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