Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-04-29
2002-10-29
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06473889
ABSTRACT:
BACKGROUND
Most computer chips are designed as a set of functional blocks where each of the functional blocks implement some small portion of the chip's overall functionality. In a floor plan design, each block is designated to be contained within its own limited area on the chip or in the silicon, which is called a constraint region. Interconnects or nets typically join individual system components within the circuit. Intra-region local nets are relatively short and are typically implemented as simple wires and connect system components within a region. However, top level nets which span blocks or cells in different constraint regions can be quite long. For even a moderately sized integrated circuit (IC), a significant number of top level wires are necessary to join system components in different blocks. These wires, used to join system components within a single block or between blocks, are quite typically resistive and passive and therefore behave as resistive capacitive (RC) transmission lines. These RC transmission lines result in delay and rise times that both increase quadratically with wire length. The longer nets experience significant signal degradation.
To mitigate the RC effects, modern chips use active repeaters within long nets to regenerate the signal. An active repeater is typically implemented as a simple buffer or inverter. Effectively, the long wires or nets are split into shorter and nominally equal length segments which are joined by these repeaters. The overall delay of the wire segments and repeaters is significantly less than for the original long wire and the rise time of the destination is also greatly improved. Typically, nets which exceed the RC limit on direct connect distance need to be divided and a repeater inserted.
In the context of repeaters, there are at least three types of net topologies that need to be considered: point-to-point, multidrop and individually buffered multidrop. Point-to-point nets simply connect one cell's output with another cell's input, so repeating a long point-to-point net by breaking the net and inserting a repeater, is straightforward. Thus, a point-to-point net which exceeds the RC limit on direct connect distance is appropriately divided and one or more repeaters are added.
When one cell's output is sent to multiple destination cells a multidrop net is present. When a multidrop net exceeds the RC limit on direct connect distances, repeaters must again be used. There are two variations of repeaters within multidrop nets: shared buffer and individually buffered cases.
In a shared buffered multidrop, a single repeater is placed between a source cell's output and the point at which the wire diverges to its multiple destinations. In an individually buffered multidrop, each destination requires a dedicated repeater so that a repeater is inserted between the point at which the wire diverges to its multiple destinations and their respective destinations. Multidrop situations can be specified as either shared buffered or individually buffered situations dependent on the specific interconnect topology, the floor plan, and by the preference of the designer. Additionally, in some multidrop nets, both shared buffered and individually buffered techniques are used. For instance, if the distance from the output to the point at which the wire diverges exceeds the RC limit on direct connect distance, a shared buffer or repeater would be needed in that segment of the wire. Additionally, if each of the individual wires from where the single wire diverges to the specific destinations, each exceed the RC limit on direct connect distances, each of these lines will need to be individually buffered with a repeater. For top level nets which are greater than twice the RC limit direct connect distance, multiple repeaters may be required.
There are a number of steps required for integrating repeaters into a higher-level (e.g. Register Transfer Logic (RTL)) design. First, a list of top level nets which may require the addition of repeaters must be generated. Second, the top level nets identified must be examined to determine the location of the repeater block constraint regions. Repeater block constraint regions are regions in which the repeater could be located and which will reduce the effective wire lengths below the RC limit on direct connect distances. The type (point-to-point, shared buffer or individually buffered multidrop) of the repeater must then be determined. When a repeater is inserted within a top level net, the net itself must be split and new net names must be created for each new piece of the original top level net. Then, a hardware description language ( HDL) description for the repeater block must be created. Finally, the repeater block input/output (I/O) ports have to be accurately wired into the original HDL model. An HDL model is a method of describing functional circuits and interconnects. Each of these manual tasks is time consuming and quite error prone. Modifications to the circuit design may necessitate the revision of repeater blocks and/or their locations. Major design modifications may require regeneration and recalculation of repeater sites.
Prior repeater insertion scripts analyze the post-placement design and calculate the length of the nets to determine if a repeater is necessary. If a repeater is necessary, a repeater insertion scripts break the net and inserts a repeater. The scripts then repeat this examination focusing on the lengths of each section of the divided net to determine if additional repeaters are necessary.
Because such repeater insertion scripts have a simplistic and “after-the-fact” (i.e., post-placement approach to repeater insertion) this technique has failed to effectively locate repeater cells to provide repeatable, controlled results. Further, the repeater insertion scripts generally do not handle multidrop topologies adequately. Additionally, this cell-level design modification invalidates the standard RTL-level design based verification and requires a gate-to-RTL equivalency check whenever the repeaters are added or modified. The resulting manual effort can be substantial.
Accordingly, a need exists for a system which automatically determines the location of the repeater blocks without expending undue time or effort. A further need exists for the automatic generation of repeater blocks which is error free. A further need exists for an automated repeater determination tool which handles multidrop topologies. Still further, a need exists for an automatic repeater determination tool which will allow design modifications without requiring manual efforts to revalidate earlier identified repeater locations.
SUMMARY OF THE INVENTION
These and other objects, features and technical advantages are achieved by a system and method which according to an aspect of the invention, a method of integrating repeaters into an integrated circuit design model includes specifying a geometry of a plurality of separate cell blocks. These cell blocks are locations on a chip die supporting appropriate functional capabilities, such as arithmetic and logic functions, decoders, input/output, etc. A list identifying top level nets connecting the cell blocks is then generated and locations along these top level nets exceeding a maximum signal transmission criteria are identified. Repeater constraint regions are defined apart from the cell blocks and include one or more of the locations identified. A list is then generated of top level nets to be repeated at respective repeater constraint regions.
According to a feature of the invention, a hardware description language (HDL) representation is automatically generated of repeater blocks for placement within each of the repeater constraint regions. Wiring directives may then be automatically generated connecting the HDL representation of repeater blocks into the integrated circuit design model.
According to another feature of the invention, the HDL representation is compatible with multiple levels of abstraction representing the integrated circu
Fiduccia Nicholas S.
Gluss Robert J.
Levin Naum
Siek Vuthe
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