Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-06-12
2002-02-05
Abraham, Fetsum (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S382000, C257S383000, C257S384000
Reexamination Certificate
active
06344675
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an SOI-MOS field effect transistor and a method of forming the same.
One of conventional SOI-MOS field effect transistors will be described with reference to
FIG. 3. A
buried oxide film
2
is provided over a silicon substrate
1
. Field oxide films
4
are selectively formed on the buried oxide film
2
. A silicon-on-insulator layer
3
made of silicon is formed over the buried oxide film
2
wherein the silicon-on-insulator layer
3
is defined by the field oxide films
4
. The silicon-on-insulator layer
3
has n-type source/drain regions
10
and
9
and a p-type body portion
5
between the n-type source/drain regions
10
and
9
. A gate oxide film
6
is provided which extends over the p-type body portion
5
and inside portions of the n-type source/drain regions
10
and
9
in the vicinity of the body portion
5
. A gate electrode
7
is provided on the gate oxide film
6
so that the gate electrode
7
is positioned over the body portion
5
. Side wall oxide films
8
are also provided on side walls of the gate electrode
7
and over the gate oxide film
6
. An inter-layer insulator
11
is further provided over the field oxide films
4
, the silicon-on-insulator layer
3
and the gate electrode
7
as well as over the side wall oxide films
8
. Contact holes
12
are formed in the inter-layer insulator
11
so that the contact holes
12
are positioned over the source/drain regions
10
and
9
. Contact layers are formed in the contact holes
12
so that the contact layers are in contact with the source/drain regions
10
and
9
. Metal interconnections
13
are provided which are connected to the contact layers so that the metal interconnections
13
are electrically connected to the source/drain regions
10
and
9
.
FIG. 1
is a graph illustrative of sub-threshold characteristics (Id-Vg characteristics) or current-voltage characteristics of the above first conventional SOI-MOS field effect transistor when applied with drain voltages of 1.5V and 0.05V. If the drain voltage of 0.05V is applied to the drain electrode of the above first conventional SOI-MOS field effect transistor, then the sub-threshold characteristic is normal and free of any kink effect. If, however, the drain voltage of 1.5V is applied to the drain electrode of the above first conventional SOI-MOS field effect transistor, then the sub-threshold characteristic exhibits a kink effect. It was known that such kink effect may appear when the drain voltage is not less than about 0.8V. The following descriptions will focus on the mechanism of the kink effect.
When the above n-channel MOS field effect transistor is in the ON-state, electrons move from the n-type source region
10
through an inversion layer in the p-type body portion
5
to the n-type drain region
9
. When electrons are injected into the drain region
9
from the inversion layer of the body portion
5
, an impact ionization is caused at a drain edge portion of the inversion layer adjacent to the drain region
9
. The impact ionization generates electron-hole pairs. Electrons generated by the impact ionization move into the drain region and are then absorbed therein, whilst the holes generated by the impact ionization are accumulated on an interface of the p-type body portion
5
to the n-type source region
10
, wherein the -type body portion
5
is electrically floated. The accumulation of the holes on the interface of the p-type body portion
5
to the n-type source region
10
rises a potential of the p-type body portion
5
. A parasitic bipolar transistor is caused. The drain region
9
virtually corresponds to the collector region. The hole accumulated interface of the body portion to the source region serve as a base region. The source region
10
serves as an emitter. When a potential difference between the hole accumulated interface of the body portion to the source region and the source region
10
is increased beyond a threshold voltage of the parasitic bipolar transistor, then the parasitic bipolar transistor turns ON. As a result, the holes accumulated on the interface of the body portion
5
to the source region
10
are injected into the source region
10
at a current Ib. The injection current of the holes from the body portion
5
to the source region
10
causes an additional current from the source region
10
to the drain region
9
through the body portion
5
is caused, wherein the additional current is defined by the product of the above current value Ib and a current amplification factor of the parasitic bipolar transistor. Such the additional current caused by the parasitic bipolar transistor causes the kink effect as well illustrated in FIG.
1
. This phenomenon is so called as a parasitic bipolar effect. In order to avoid this parasitic bipolar effect, it is effective to allow a leakage of current between the body portion and the source region so that the holes accumulated on the interface of the body portion to the source region
5
are allowed to flow into the source region
10
, thereby to suppress the increase in potential of the body portion. Alternatively, it is also effective to decrease the current amplification factor of the parasitic bipolar transistor so as to decrease the additional current whereby the kink effect is suppressed.
In the Japanese laid-open patent publication No. 2-291175, there is disclosed a second conventional SOI-MOS field effect transistor, descriptions of which will hereinafter be made with reference to
FIG. 4. A
buried oxide film
2
is provided over a silicon substrate
1
. Field oxide films
4
are selectively formed on the buried oxide film
2
. A silicon-on-insulator layer
3
made of silicon is formed over the buried oxide film
2
wherein the silicon-on-insulator layer
3
is defined by the field oxide films
4
. The silicon-on-insulator layer
3
has n-type source/drain regions
10
and
9
and a p-type body portion
5
between the n-type source/drain regions
10
and
9
. A gate oxide film
6
is provided which extends over the p-type body portion
5
and inside portions of the n-type source/drain regions
10
and
9
in the vicinity of the body portion
5
. A gate electrode
7
is provided on the gate oxide film
6
so that the gate electrode
7
is positioned over the body portion
5
. Side wall oxide films
8
are also provided on side walls of the gate electrode
7
and over the gate oxide film
6
. A metal layer
15
is further provided which extends over the gate insulation film in the source side and over the source region
10
except in the vicinity of the body portion
5
. An inter-layer insulator
11
is further provided over the field oxide films
4
, the metal layer
15
, the silicon-on-insulator layer
3
and the gate electrode
7
as well as over the side wall oxide films
8
. Contact holes
12
are formed in the inter-layer insulator
11
so that the contact holes
12
are positioned over the metal layer
15
over the source region
10
and over the drain region
9
. Contact layers are formed in the contact holes
12
so that the contact layers are in contact with the metal layer
15
over the source region
10
and the drain region
9
. Metal interconnections
13
are provided which are connected to the contact layers so that the metal interconnections
13
are electrically connected to the source/drain regions
10
and
9
.
The metal layer
15
has a lower resistivity than that of the source region
10
. The provision of the metal layer
15
allows a leakage of current of holes or promotes that holes accumulated on the interface of the body portion
5
to the source region
10
are injected to the metal layer
15
. Such leakage of the holes from the body portion to the source region results in a potential drop of the body portion. This prevents the increase in potential of the body portion. The suppression of the increase in potential of the body portion prevents the increase in potential difference between the body portion and the source region beyond the threshold voltage. This prevents
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