Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1999-06-24
2002-06-18
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S141000
Reexamination Certificate
active
06408362
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to data processing and, in particular, to a cache coherency protocol for a data processing system. Still more particularly, the present invention relates to a cache coherency protocol including one or more states that indicate the access latency of a memory copy of cached data in a data processing system.
2. Description of the Related Art
It is well-known in the computer arts that greater computer system performance can be achieved by harnessing the processing power of multiple processors in tandem. Multiprocessor (MP) computer systems can be designed with a number of different architectures, of which various ones may be better suited for particular applications depending upon the performance requirements and software environment of each application. One of the most common MP computer topologies is a symmetric multiprocessor (SMP) configuration in which multiple processors share common resources, such as a system memory and input/output (I/O) subsystem, which are typically coupled to a shared system interconnect. Such computer systems are said to be symmetric because all processors in an SMP computer system ideally have the same access latency with respect to data stored in the shared system memory.
Although SMP computer systems permit the use of relatively simple inter-processor communication and data sharing methodologies, SMP computer systems have limited scalability. In other words, while performance of a typical SMP computer system can generally be expected to improve with scale (i.e., with the addition of more processors), inherent bus, memory, and input/output (I/O) bandwidth limitations prevent significant advantage from being obtained by scaling a SMP beyond a implementation-dependent size at which the utilization of these shared resources is optimized. Thus, the SMP topology itself suffers to a certain extent from bandwidth limitations, especially at the system memory, as the system scale increases.
In order to overcome scalability limitations of conventional symmetric multiprocessor (SMP) data processing systems and to improve access latency to system memory, some recent MP architectures distribute system memory within a computer system such that a processor's access paths and access latencies to data vary for different portions of the distributed system memory. The present invention recognizes that such non-symmetric architectures are also subject to a number of inefficiencies. In particular, the present invention recognizes that such non-symmetric architectures do not account for the varying access latencies among the various portions of the distributed system memory in implementing cache line deallocation and victim selection policies.
SUMMARY OF THE INVENTION
To overcome the above-noted and other shortcomings of the prior art, the present invention introduces the concept of storing, in association with cached data, an indication of the access latency of a memory copy of the cached data.
A data processing system in accordance with the present invention includes a processing unit, a distributed memory including a local memory and a remote memory having differing access latencies, and a cache coupled to the processing unit and to the distributed memory. The cache includes a congruence class containing a plurality of cache lines and a plurality of latency indicators that each indicate an access latency to the distributed memory for a respective one of the cache lines. The cache further includes a cache controller that selects a cache line in the congruence class as a castout victim in response to the access latencies indicated by the plurality of latency indicators. In one preferred embodiment, the cache controller preferentially selects as castout victims cache lines having relatively short access latencies.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 4314331 (1982-02-01), Porter et al.
patent: 4496539 (1985-01-01), Vosacek
patent: 5623632 (1997-04-01), Liu et al.
patent: 5706465 (1998-01-01), Kurokawa et al.
patent: 5787471 (1998-07-01), Inoue
patent: 5895486 (1999-04-01), Patel
patent: 6141734 (2000-10-01), Razdan et al.
patent: 6154816 (2000-11-01), Steely et al.
patent: 6173364 (2001-01-01), Zenchelsky et al.
U.S. application No. 09/339,403, Arimilli et al., filed Jun. 24, 1999.
Arimilli Lakshminarayana Baba
Arimilli Ravi Kumar
Fields, Jr. James Stephen
Ghai Sanjeev
Bracewell & Patterson L.L.P.
Chace Christian P.
International Business Machines - Corporation
Kim Matthew
Salys Casimer K.
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