Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2000-09-28
2002-12-31
Fahmy, Jr., Wael (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S151000, C438S153000, C438S154000, C438S159000, C257S059000, C257S066000
Reexamination Certificate
active
06500700
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabrication method of an active matrix type liquid crystal display having a thin film transistor as a switching element.
2. Description of the Related Art
A liquid crystal display has a feature to be light, a thin type and low power consumption, and is applied to a variety of areas such as a portable terminal, a finder of a video camera, a display of a notebook personal computer. Among them, an active matrix type liquid crystal display can display high quality and fine images, thereby being used for large displays for computers and the like. From now on, the more and more increase of the demands for the active matrix type liquid crystal display leads to the establishment of the fabrication method of the liquid crystal display having a high productivity at a low cost.
The conventional liquid crystal display and the fabrication method thereof are described with reference to FIG.
7
through FIG.
10
. First, a schematic structure of the active matrix type liquid crystal display fabricated by the fabrication method of the conventional liquid crystal display is described with reference to FIG.
7
.
FIG. 7
shows a plan view of the substrate viewing an array substrate from the liquid crystal layer side. In
FIG. 7
, gate bus lines, the drain bus lines, and external connecting terminal areas of the bus lines for storage capacitors are shown along with the illustration of the pixel areas, omitting the intermediate illustration. As shown in
FIG. 7
, a plurality of drain bus lines
112
extending in the vertical direction in the diagram are formed on the array substrate. Further, on the array substrate, a plurality of gate bus lines
102
extending in the horizontal direction in orthogonal with the drain bus lines
112
in the diagram are formed. Areas decided by these drain bus lines
112
and gate bus lines
102
are pixel areas.
A sandwiching drain type TFT
100
is formed adjacent to the intersection position between the drain bus line
112
and the gate bus line
102
in each pixel area. A drain electrode
107
of the sandwiching drain type TFT
100
is pulled out from the drain bus line
112
and its edge is positioned on one edge side on an active semiconductor layer
104
(not shown in
FIG. 7
) on the gate bus line
102
. At the same time, the end portion is formed crossing on the gate bus line
102
to prevent the signal mixing from the adjacent drain bus line. This drain electrode structure has a structure which sandwiches the area of the gate bus line
102
functioning as a gate electrode of the TFT
100
in the pixel area between the drain bus line
112
and the drain electrode
107
. The active semiconductor layer
104
is formed above the gate bus line
102
and along the gate bus line
102
and ordinary is required to be electrically separated from the active semiconductor
104
of the TFT
100
in the other adjacent pixel area. However, according to such a sandwiching drain electrode structure, there is a merit that the patterning of the active semiconductor layer
104
for the TFT element separation between each pixel is not required and the number of the masks can be reduced in the photolithography process.
A source electrode
106
is formed on the other edge side on the active semiconductor layer
104
to oppose to the drain electrode
107
. The source electrode
106
is electrically connected with a pixel electrode
114
formed along a shape of the pixel area. In the TFT structure shown in
FIG. 7
, the gate electrode is not formed by pulled out from the gate bus line
102
. Therefore, the gate bus line
102
area arranged just under the active semiconductor layer
104
at the lower layer of source electrode
106
and the drain electrode
107
functions as the gate electrode
102
of the TFT
100
. Although the illustration is omitted, a gate insulating film
103
is formed between the gate bus line
102
and the active semiconductor layer
104
thereon.
At the lower layer of the pixel electrode
114
, a storage capacitor wiring
150
is formed in parallel with the gate bus line
102
and crosses substantially the center of the pixel electrode
114
. A semiconductor layer (herein after referred to the active semiconductor layer
104
for convenience' sake) is formed simultaneously with the active semiconductor layer
104
at the upper layer of the storage capacitor wiring
150
. Therefore, it is required to electrically separate the semiconductor layer from the active semiconductor layer
104
on the storage capacitor wiring
150
in the other adjacent pixel area, and therefore a pixel separation area
162
is formed in an area between the drain bus line
112
and the pixel electrode
114
where the active semiconductor layer
104
is removed.
Further, an external connecting terminal
152
for an electrical connection with an external element is provided at one end portion of the drain bus line
112
. Similarly, an external connecting terminal
154
for an electrical connection with an external element is provided at one end portion of the gate bus line
102
and an external connecting terminal
156
is formed at one end portion of the storage capacitor wiring
150
. In
FIG. 7
, a short ring (a common electrode)
158
for an electrical connection between the external connecting terminal
154
of each gate bus line
102
is formed for an electrostatic protection in the fabrication process of the array substrate. Furthermore, a leading electrode
159
for the storage capacitor wirings is formed serving also as a common electrode. Although an illustration is omitted, a short ring electrically connecting each external connecting terminal
152
of the drain bus line
112
is separately formed. The short rings of these drain bus line and gate bus line, for example a short ring
158
, are cut at the position of a dashed line
160
in FIG.
7
and separated after the array substrate and the opposing substrate are laminated.
Next, the conventional fabrication method of the liquid crystal display is described with reference to
FIG. 8A
a
through FIG.
10
.
FIG. 8A
a
through
FIG. 9C
c
show partial cross sections showing the conventional fabrication process of the liquid crystal display.
FIGS. 8A
a
,
8
A
b
,
8
A
c
,
9
A
a
,
9
A
b
and
9
A
c
show cross sections adjacent to the TFT
100
cut at a line A-A′ in FIG.
7
.
FIGS. 8B
a
,
8
B
b
,
8
B
c
,
9
B
a
,
9
B
b
and
9
B
c
show cross sections adjacent to the element separation area cut at a line B-B′ in FIG.
7
.
FIGS. 8C
a
,
8
C
b
,
8
C
c
,
9
C
a
,
9
C
b
and
9
C
c
show cross sections of the external connecting terminal
154
of the gate bus line
102
cut at a line C-C′ in FIG.
7
.
Now, as shown in
FIGS. 8A
a
,
8
B
a
and
8
C
a
, a metal thin film
164
depositing Al film and a Ti film thereon in this order is formed on a transparent insulating substrate (a transparent glass substrate)
110
of, for example, 0.7 mm in thickness as the array substrate by a sputtering method. Next, the gate insulating film
103
is formed by depositing for example a silicon nitride (SiN) film on the whole substrate surface by a plasma CVD method. Next, for example an amorphous silicon (a-Si) layer
166
for forming the active semiconductor layer
104
is deposited on the whole substrate surface by the plasma CVD method. Further, a n
+
a-Si layer
168
adding for example phosphorus (P) is formed on the whole substrate surface by the plasma CVD method to form a low resistance semiconductor layer
105
to be an ohmic contact layer.
Next, after resist is coated on the whole surface, the resist is patterned in a shape of the gate bus line and a shape of the storage capacitor wiring using a first resist exposure mask. The layers are etched together up to the metal thin film
164
using chlorine type gas by for example a reactive ion etching using the patterned resist layer (not shown) as a first etching mask, thereby as shown in
FIGS. 8A
b
,
8
B
b
and
8
C
b
areas for the gate bus line
102
and the
Fahmy Jr. Wael
Fujitsu Limited
Greer Burns & Crain Ltd.
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