Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
1999-04-16
2002-11-05
Wong, Peter (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S300000, C710S314000
Reexamination Certificate
active
06477611
ABSTRACT:
TECHNICAL FIELD
The present invention relates in general to buses used in electronic devices. More particularly, the present invention pertains to input/output bus systems used by electronic devices and modules. More specifically, the present invention relates to apparatus and methods used to interconnect electronic devices and modules with input/output buses having incompatible mechanical, electrical and/or logical characteristics.
BACKGROUND ART
Electronic devices such as digital computers employ a variety of internal and external buses to facilitate communication and information transfer between the various circuits or other components thereof, and other external electronic devices, which may be referred to as modules. A special class of buses, referred to as input/output (I/O) buses, have been developed to interconnect electronic devices such as digital computers with external modules. Often these buses, and, in particular, I/O buses, are configured with mechanical, electrical and/or logical characteristics optimized for the circuits and components they contain, or the application(s) they perform, and are incompatible with the buses of other electronic devices, limiting, sometimes severely, the modules with which an electronic device may be used.
This problem has been particularly vexing to computer owners and manufacturers of modules such as so-called add-in boards or peripherals that add significant functionality to a general-purpose computer. Add-in boards purchased by computer owners for one computer will not work with other computers unless the buses are the same. Manufacturers must either forgo universal compatibility, or design and inventory several versions of an add-in board to meet the needs of customers with a variety of computers having incompatible buses. Thus, for example, when a new computer having a different I/O bus is introduced, older “legacy” add-in boards and other modules cannot be moved to the new computer.
Various designs have been put forth in an attempt to minimize inoperability of electronic devices and modules having incompatible buses. Generally these designs involve predefining a limited number of bus configurations, imbuing the devices with all possible configurations, and devising some mechanism by which a common configuration may be selected. At first the compatible bus configuration was selected manually by the user, such as with the setting of a manual switch or the manual insertion or removal of jumper wires.
Another approach, employed in U.S. Pat. No. 5,655,148 to Richman et al. and marketed as “plug-n-play”, involved assigning every add-in board a unique identification (ID) number, and storing it in an on-board, non-volatile memory. Every electronic device would require an on-board database of all ID numbers and the fixed bus structure associated with it. Startup of the electronic device would include checking the ID numbers for all connected add-in boards, and loading from onboard memory the resources necessary for interface. However, as many users discovered, add-in boards frequently would not interface successfully because they were not assigned an ID number, had a non-unique ID number, had an ID number not in the memory of the electronic device, or had interface physical characteristics differing from that of the electronic device.
More recently, designs for the automatic sensing and switching of bus configuration have been disclosed. One example of this technique involves the use of field programmable gate arrays (FPGAs) to allow the reconfiguration of selected bus pins. For example, in U.S. Pat. No. 5,734,872 to Kelly a system is disclosed for swapping CPUs chosen from a preselected group in and out of computers with a fixed system bus. Configuration information is stored in a read only memory. When the CPU is swapped, the signals on each pin are sampled to identify the CPU bus configuration, and the FPGA reconfigured to conform with the new CPU configuration.
Another approach is disclosed in U.S. Pat. No. 5,594,874 to Narayanan et al., where a unit for interfacing the integrated circuit package connector pins with a computer system bus can support three different, predefined bus structures using the same connector pins for different functions. A single pin on the integrated circuit, called the Address Strobe pin (ASP), is used to automatically detect a signal level representative of the bus structure to be used. As shown in FIG. 2 of the Narayanan et al. patent, if the logic level on the ADS pin is low, the other integrated circuit connector pins are configured for IBM's Industry Standard Architecture (ISA) bus configuration. If the logic level on the ADS pin is high, the other integrated circuit connector pins are configured for Intel's PI bus configuration; and if the logic level is in transition between low and high, the other integrated circuit connector pins are configured for the Video Electronics Standard Association's Local (VL) bus configuration.
Devices such as the Narayanan et al. interface unit still require that all interface characteristics be predefined and known to both the electronic device and the module with which it is desired to interconnect. These devices can only work with a very few bus configurations, the selection of which cannot be altered once chosen. The cost of the interface unit increases significantly with each additional preselected bus configuration to be made available.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide an apparatus and method for establishing compatibility between at least two incompatible I/O buses without a previously defined, common bus configuration.
It is another object of the present invention to provide an apparatus and method for establishing compatibility between at least two incompatible I/O buses, as set forth above, wherein said compatibility is established automatically without user intervention.
It is still another object of the present invention to provide an apparatus and method for establishing compatibility between at least two incompatible I/O buses, as set forth above, wherein compatibility may be established between a limitless number of incompatible I/O buses.
It is yet another object of the present invention to provide an apparatus and method for establishing compatibility between at least two incompatible I/O buses, as set forth above, wherein an I/O bus configuration selected to establish compatibility may be changed at any time to another compatible configuration.
It is a further object of the present invention to provide an apparatus and method for establishing compatibility between at least two incompatible I/O buses, as set forth above, in which cost does not increase as the number of compatible I/O bus configurations increases.
These and other objects and advantages of the present invention over existing prior art forms will become more apparent and fully understood from the following description in conjunction with the accompanying drawings.
In general, an apparats for establishing compatibility between at least two input/output buses includes a first device having a first input/output, bus with an adaptable, first configuration, and a second device having a second input/output bus incompatible with said input/output bus and with a second configuration and a memory including the location of configuration information characterizing the second configuration. The location of configuration information is communicated from the second device to the first device. The first device further includes. a processor receiving said location of configuration information from the second device, retrieving the configuration information using the location of configuration information, and reconfiguring the first input/output bus to be compatible with the second input/output bus.
A method for establishing compatibility between at least two input/output buses including a first device having a first input/output bus with an adaptable, first configuration, and a second device having a second input/output bus incompa
Accellent Systems Inc.
Robbins Howard S.
Vo Tim
Wong Peter
LandOfFree
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