Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2001-04-25
2002-08-27
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S210130, C365S207000
Reexamination Certificate
active
06442081
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor memory devices and more particularly to a semiconductor memory device having a serial access mode that includes a latency period and a serial access period.
BACKGROUND OF THE INVENTION
In order to improve operation speeds, semiconductor memory devices can have a serial access mode of operation. In a serial access mode of operation, a read command is received by the semiconductor memory. Then, after a latency period, data is read out in a serial fashion.
A serial access mask ROM (read only memory) has a serial access mode of operation. When a serial access mask ROM receives a read command, a word line is activated based on a received address. The time required to activate the word line and access the first bits of data is defined as the latency period. The time to access subsequent bits of data in a sequential fashion can be called a serial access period. The data can be serially accessed synchronously with an external read clock signal that is applied to the semiconductor memory device.
In a semiconductor memory device having such a serial access mode, the data transfer speed can be improved by shortening the latency period. The latency period can be shortened by providing a faster access to the first bits of data. The data transfer speed can also be improved by shortening the access times during the serial access period.
Another factor in the design of a semiconductor memory device is chip size. In order to reduce chip size, the word line length is made as long as possible, which reduces the number of row decoders needed. Because bits are typically accessed serially from the same word line, lengthening the word line can also allow more bits to be serially accessed in one serial access mode operation. However, this can effect the latency period because a longer word line is slower to rise due to the larger resistive and capacitive load.
Memory cells in a serial access mask ROM can be programmed in one of two different states. The programmed state indicates whether the data value stored in the memory cell is logic one or logic zero. The states of the memory cell can be termed as an ON-cell or an OFF-cell. An on-cell is a memory cell that has been programmed to be conductive when selected by a word line. An OFF-cell is a memory cell that has been programmed to be non-conductive when selected by a word line. Each memory cell is typically an n-channel insulated gate field effect transistor (IGFET), which can be programmed to be an OFF-cell by programming a high threshold voltage or to be an ON-cell by programming a low threshold voltage. This can be done with an ion implantation step, as just one example. In this example, it is assumed that the memory cell is a NAND type cell.
An example of a conventional serial access mask ROM will now be described with reference to a sense amplifier set forth in
FIG. 3 and a
timing diagram set forth in FIG.
5
. The conventional serial access mask ROM has a serial mode of operation in which there is a latency period and serial access period.
Referring now to
FIG. 3
, a sense amplifier is set forth in a circuit schematic diagram and given the general reference
110
. The sense amplifier detects whether a selected memory cell is an ON-cell or an OFF-cell by comparing a sense level at a sense node N
306
with a reference voltage REF. This is done by having sense node N
306
and reference voltage REF as inputs to differential amplifier
304
. Differential amplifier
304
provides a data output SOUT based on the comparison. In the conventional serial mask ROM, the reference voltage is at a midpoint of the voltage swing of the sense node N
306
.
Differential amplifier
304
can be electrically connected to a selected memory cell by a column selector and memory cell digit lines
307
by way of a input node N
305
. When a memory cell is selected, the state of the memory cell (ON-bit or OFF-bit) determines the potential of sense node N
306
.
Referring now to
FIG. 5
, waveforms indicating a serial access mode operation of a conventional serial access ROM are set forth. The waveforms pertaining to a serial access mode operation of a conventional serial access ROM are labeled as “BACKGROUND ART.”
FIG. 5
represents a serial access mode read operation and illustrates the latency period and serial access period.
At time t
2
, conventional serial access ROM enters the latency period in which a word line is selected based on the address that has been applied. It is noted that in the conventional serial access ROM, digit lines adjacent to the digit line associated with the selected cell are discharged to ground in order to prevent excessively charging of digit lines.
Thus, at time t
2
, based on the received row address, a word line is selected. At the same time, a digit line is selected based on a received column address. Thus, the selected word line can begin to rise. The potential of the selected digit line can begin to rise also. This is due to the p-channel load IGFET
301
in the sense amplifier
110
illustrated in FIG.
3
. However, due to the word line having a larger capacitive and/or resistive load, the selected word line rises at a slower rate than the selected digit line.
Assuming that the first bit read during the latency period is an ON-cell, once the word line achieves a high enough voltage to turn on the n-channel IGFET memory cell, the selected digit line begins to discharge. It is noted that because the digit-line charges up during the precharge period before the word line rises to a sufficient level to turn on the ON-bit selected memory cell, the sense node N
306
can achieve a relatively high precharge voltage.
After the word line reaches a high enough voltage for the selected ON-cell to conduct, the digit line can be discharged toward a ground level. This can be seen as dashed line of SENSE LEVEL signal (corresponding to sense node N
306
) in the BACKGROUND art waveforms of FIG.
5
. When the sense node N
306
reaches a level below the voltage reference REF, the sense amplifier
110
can correctly produce a sense amp output SOUT at a logic level (high in this case) corresponding to an ON-bit cell.
Next, at time t
3
, a clock RCLOCK makes a transition, which is the beginning of the serial access portion of the serial access mode. A column address is incremented and a different digit line is selected. During this read cycle, the memory cell associated with the selected digit line and already selected word line is an off-bit cell. The OFF-bit cell does not conduct current and the digit line can be pulled up by the p-channel load transistor
301
. Once the SENSE LEVEL signal (sense node N
306
) reaches a voltage level above the voltage reference REF, the sense amplifier
110
can correctly produce a sense amp output SOUT at a logic level (low in this case) corresponding to an OFF-bit cell.
It is noted that the drive strength of p-channel load transistor
301
decreases as the digit line rises. This is because the gate to source voltage is decreased. Thus, although the digit line may rise relatively fast at first, the drive strength can decrease as the digit line potential gets closer to the reference voltage VREF. Thus, the reading of the OFF-bit cell can be slow.
Illustrated in the read cycle between times t
3
and t
4
, is a dashed waveform which can correspond to an ON-bit cell being read. It can be seen from the sense amp output SOUT, that an ON-bit cell can be read faster than an OFF-bit cell in the serial access portion of a serial access mode. However, compared to the latency portion, it can be seen from the sense amp output SOUT, that an OFF-bit cell is read faster than an ON-bit cell in the serial access portion of a serial access mode.
The access time of a semiconductor memory device is determined by the slowest bit read. Thus, the access time is limited when one type of bit is read more slowly under certain conditions.
In view of the above discussion, it would be desirable to provide a semiconductor device having a serial access mode of operation in which a
Ho Hoai
Le Thong
NEC Corporation
Walker Darryl G.
LandOfFree
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