Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
1999-12-15
2002-10-01
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S012000, C710S048000, C710S054000, C710S068000
Reexamination Certificate
active
06460095
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data transfer apparatus and a data transfer system intended to transfer data continuously input or output to/from a main memory without any omission. In particular, the present invention relates to a data transfer apparatus and a data transfer system that transfer continuous data on a general-purpose bus such as a PCI bus. The present invention also relates to a recording medium storing a program that commands a computer to execute all or some of functions of each component of the data transfer apparatus or data transfer system.
2. Description of the Prior Art
As a conventional system that transfers data input/output to/from external devices with a main memory connected to a system bus, a PCI bus used by a personal computer is known (OPEN DESIGN No. 7 “Details of PCI Bus and Steps for its Applications” CQ Publishing Co., Ltd.).
FIG. 15
shows a system block diagram of the PCI bus and with reference now to the attached drawings a data transfer example of the PCI bus will be explained below.
In
FIG. 15
,
101
is a central processing unit (hereinafter referred to as “CPU”),
102
is a main memory and
103
is a memory controller that controls the main memory
102
, and these are connected by a host bus
104
.
105
is a host PCI bridge,
106
is an I/O device,
107
is a PCI board having a device that allows data input/output to/from external devices,
109
is an extended bus bridge and
108
is a PCI bus that connects these.
110
is a PCI bus controller that controls the PCI bus,
111
is a buffer memory that stores input data temporarily and
112
is a buffer controller.
When data is input from the input terminal of a PCI board
107
, the data is temporarily stored in a buffer memory
111
. The amount of data stored in the buffer memory
111
is controlled by a buffer controller
112
and if a predetermined amount of data is reached, a transfer request is issued to the PCI bus controller
110
. After receiving the transfer request from the buffer controller
112
, the PCI bus controller
110
issues a bus access request signal onto the PCI bus
108
. The bus access request signal is transmitted to the host PCI bridge
105
and enables the PCI board
107
to access the PCI bus
108
if there is no access request from other PCI boards. Given the access right, the PCI bus controller
110
issues a transfer enable to the buffer controller
112
and immediately starts a data transfer from the buffer memory
111
. The data transferred from the PCI board
107
is temporarily stored in the host PCI bridge
105
and stored in the main memory
102
through the host bus
104
and the memory controller
103
.
As shown above, the conventional example above with the buffer memory
111
can temporarily store data input from external devices until the right of access to the PCI bus
108
is given and transfer all data to the main memory
102
without any omission. The data stored in the main memory
102
is transformed to various formats by the CPU
101
.
In a personal computer, an add-on card and mother board are connected by a communication path, which is a so-called computer bus such as PCI interface, and the electrical characteristics and the signal format of a computer bus are often made open to general public, which originates great problems such as illegal copies of digital information transmitted through the above computer bus and subsequent data alteration.
BRIEF SUMMARY OF THE INVENTION
Object of the Invention
However, performing a continuous input/output data transfer between external devices and the main memory on the conventional PCI bus involves the following problems:
First, various kinds of PCI boards are connected to the PCI bus
108
, each PCI board issues a request for access to the PCI bus
108
at irregular time intervals and transfers data of undefined lengths, which makes irregular intervals at which access to the PCI bus
108
is permitted. If it occurs frequently that the access enable issuance time interval exceeds the value obtained by dividing the capacity of the buffer memory
111
by the transfer rate of continuously input/output data, then the continuously input/output data will overwrite (when input to the main memory
102
) on the buffer memory
111
, resulting in data omissions or the buffer memory
111
becoming empty (when output from main memory
102
) leading to an empty transfer.
Moreover, since the PCI bus
108
is a general-purpose bus, if data input is video/voice data, the PCI bus
108
easily allows other PCI boards or I/O devices to incorporate the input data, which causes another problem of easily allowing illegal copies.
The present invention has taken into account the problems above of the conventional PCI bus transfer system and it is an objective of the present invention to provide a data transfer apparatus and data transfer system capable of preventing continuously input/output data from being interrupted even if bus access enable issuance time intervals become irregular.
SUMMARY OF THE INVENTION
The 1st invention of the present invention is a data transfer apparatus temporarily storing continuously input data and transmitting the input data to a transfer destination according to an input enable signal issued by said transfer destination through a first bus, comprising:
an input buffer memory that temporarily stores said continuously input data;
a transfer controller, connected with said transfer destination through said first bus, that acquires said input enable signal through said first bus and transmits said temporarily stored input data output from said input buffer memory to said transfer destination through said first bus;
a second bus that performs data transfer between said input buffer memory and said transfer controller; and
a buffer controller that controls the output of said input buffer memory according to said input enable signal,
wherein said input buffer memory capacity CAPW satisfies the following Mathematical formula 1, where the input rate of said continuously input data is T
1
and the maximum assumed value of the transmission time interval of said input enable signal issued by said transfer destination is TW:
CAPW
≧
TW
×
T1
[
Mathematical
formula
1
]
The 2nd invention of the present invention is a data transfer apparatus temporarily storing output data transmitted from a transfer destination through a first bus according to an output enable signal issued by said transfer destination and continuously outputs the data, comprising:
a transfer controller connected with said transfer destination through said first bus that acquires said output enable signal and said transmitted output data through said first bus;
an output buffer memory that temporarily stores and continuously outputs said transmitted output data;
a second bus that performs data transfer between said output buffer memory and said transfer controller; and
a buffer controller that controls the input to said output buffer memory according to said output enable signal,
wherein said output buffer memory capacity CAPR satisfies the following Mathematical formula 2, where the output rate of said continuously output data is T
2
and the maximum assumed value of the transmission time interval of said output enable signal issued by said transfer destination is TR:
CAPR
≧
TR
×
T2
[
Mathematical
formula
2
]
The 3rd invention of the present invention is a data transfer apparatus temporarily storing continuously input data, transmitting the input data to a transfer destination through a first bus according to an input enable signal issued by said transfer destination and temporarily storing output data transmitted from said transfer destination through the first bus according to an output enable signal issued by said transfer destination and continuously outputs the output data, comprising:
an input buffer memory that temporarily stores said continuously input data;
an
Komeno Junichi
Ueno Takafumi
Farooq Mohammad O.
Smith , Gambrell & Russell, LLP
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