Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2001-05-04
2002-06-11
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000, C365S185090
Reexamination Certificate
active
06404683
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device such as an electrically programmable nonvolatile memory with redundant memory cells for replacement of defective memory cells, and to the testing of such a semiconductor memory device.
There are various types of electrically programmable nonvolatile memory, including one-time programmable (OTP) read-only memory (ROM), which can be programmed but not erased; erasable programmable read-only memory (EPROM), which can be erased by exposure to ultraviolet light; and electrically erasable programmable read-only memory (EEPROM), which can be both programmed and erased electrically. An OTP ROM and an EPROM may be structurally the same, but the EPROM is housed in a package that admits ultraviolet light, while the OTP ROM is housed in a package that does not admit ultraviolet light. In this case, the data in an OTP ROM are erasable at the factory, before the device is packaged, but cannot be erased once the device has been shipped as a product. An OTP ROM is typically enclosed in an inexpensive plastic package, while an EPROM requires a more expensive windowed ceramic package.
Incidentally, OTP ROM is sometimes referred to by various other names, such as PROM (programmable ROM).
FIG. 8
shows a block diagram of a conventional OTP ROM or EPROM device. The device comprises a main cell array
10
, an address buffer (AD. BUF.)
11
, a plurality of address input terminals
12
, a row decoder (DEC.)
13
, a plurality of word lines
14
, a column (COL.) decoder
15
, a column switch circuit
16
, a plurality of bit lines
17
, a data input-output circuit
18
, at least one data input-output terminal
19
, a control circuit
20
, a plurality of control signal input terminals
21
, a redundancy fuse circuit (CKT)
22
, a redundant address buffer (RED. AD. BUF.)
23
, a redundancy decoder (RED. DEC.)
24
, at least one redundant word line
25
, a redundant cell array
26
, and a non-select signal line
27
.
The main cell array
10
and redundant cell array
26
are arrays of nonvolatile memory cells. Each memory cell comprises, for example, a field-effect transistor with a floating gate. The cell is programmed to the ‘0’ state by injection of electrons into the floating gate, and erased to the ‘1’ state by removal of electrons from the floating gate; these operations change the threshold voltage of the transistor. The programming operation is carried out by applying predetermined voltages to the memory cell; the erasing operation is carried out by exposure to ultraviolet light.
A memory cell is selected for programming or read access by selecting the bit line
17
and the word line
14
or redundant word line
25
to which the cell is connected. Only one word line
14
or redundant word line
25
is selected at a time, but when bit lines
17
are selected, n bit lines are selected simultaneously, where n is the number of data input-output terminals
19
. Programming and read access are thus carried out n bits at a time; n is referred to as the data width.
The nonvolatile memory cells in the main cell array
10
will be referred to below as main memory cells, or simply as main cells. The nonvolatile memory cells in the redundant cell array
26
will be referred to as redundant memory cells, or simply as redundant cells.
The address signals received at the address input terminals
12
include a row address and a column address. Both the row and column addresses are stored simultaneously in the address buffer
11
. Normally, the row decoder
13
decodes the row address and thereby selects one of the word lines
14
. The column decoder
15
decodes the column address and supplies decoded signals to the column switch circuit
16
, which selects a corresponding group of n bit lines
17
. In this way n main memory cells are selected.
When data are programmed into the selected memory cells, n bits of data are supplied to the data input-output terminals
19
and passed in parallel through the data input-output circuit
18
to a programming circuit (not visible) in the column switch circuit
16
, which places the data on the n selected bit lines
17
. The data are programmed by the application of suitable voltages to the selected word line
14
and bit lines
17
.
When data are read from the selected memory cells, n bits of data are passed in parallel from the memory cells through the column switch circuit
16
to sense amplifiers (not visible) in the data input-output circuit
18
, then output from the data input-output terminals
19
.
A word line
14
having one or more defective memory cells is replaced with a redundant word line
25
by cutting corresponding fuses (not visible) in the redundancy fuse circuit
22
, thereby programming the redundancy fuse circuit
22
with the row address of the word line. This process is referred to as redundancy repair, and the row addresses programmed into the redundancy fuse circuit
22
will be referred to as redundancy repair addresses. After redundancy repair, when an address is received at the address input terminals
12
and stored in the address buffer
11
, if the row address bits do not match any redundancy repair address, the row address is decoded by the row decoder
13
as described above to select a word line
14
, but if the row address bits match a redundancy repair address, the redundancy decoder
24
drives the non-select signal line
27
, thereby disables the row decoder
13
, and selects a redundant word line
25
. As a result, n redundant memory cells on the selected redundant word line
25
are accessed (programmed or read).
Before redundancy repair is performed, the redundant cell array
26
may need to be tested to check that the redundant cells themselves are not defective. During this test procedure, the control circuit
20
controls the redundancy decoder
24
to select the redundant word lines
25
.
FIG. 9
is a flowchart of a conventional procedure for testing the memory cells and performing redundancy repair. The test procedure is carried out on a wafer on which a plurality of nonvolatile memory devices have been formed. The test apparatus, referred to below as a tester, has electrodes for accessing (‘probing’) the address input terminals
12
, data input-output terminals
19
, and control signal input terminals
21
of each memory device on the wafer. The procedure comprises a first probing step S
1
, a fuse-programming step S
2
, an ultraviolet (UV) erasing step S
3
, a second probing step S
4
, a wafer baking step S
5
, a third probing step S
6
, and another ultraviolet erasing step S
7
. The first probing step S
1
includes sub-steps S
101
to S
104
. The second probing step S
4
includes sub-steps S
401
and S
402
. The third probing step S
6
includes a single sub-step S
601
.
At the beginning of the procedure all memory cells are nominally in the erased (‘1’) state.
The first probing step S
1
is carried out as follows. In sub-step S
101
, all memory cells in the main cell array
10
are read to check that they are in the ‘1’ state. This is referred to as a ‘1’ read test (a read test with the expected value ‘1’). Next, in sub-step S
102
, all memory cells in the main cell array
10
are programmed to the ‘0’ state and a ‘0’ read test is performed (a read test with the expected value ‘0’). The redundant memory cells are not tested at this stage.
Next, in sub-step S
103
, the row addresses of any defective main memory cells found in the preceding sub-steps are stored in the tester. Then in sub-step S
104
, the tester decides whether redundancy repair is necessary, and if necessary, whether it is feasible; that is, whether there are enough redundant word lines
25
to replace all the word lines
14
having defective memory cells.
If redundancy repair is necessary and feasible, then the redundancy fuse circuit
22
is programmed in step S
2
by cutting fuses corresponding to the row addresses of the defective memory cells. This step replaces the defective main memory cells with redundant memory cells.
Following these steps, the wafer is exposed t
Nguyen Tan T.
Oki Electric Industry Co. Ltd.
Rabin & Berdo P.C.
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