Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-03-17
2002-08-13
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S506000, C257S513000, C257S752000, C438S620000, C438S624000, C438S637000
Reexamination Certificate
active
06433372
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit devices using Field Effect Transistors (FETs), and more particularly, to reduced parasitic capacitance of multigate MOSFET structures and methods of making the same.
2. Description of Related Art
Field effect transistor devices have become increasingly important in low voltage power application designs. However, semiconductor device parameters such as threshold voltage, sub-threshold leakage currents, and parasitic capacitances, typically source and drain parasitics, limit the performance of these FETs in the semiconductor device application.
Modern process technologies, such as shallow trench isolation and silicon-on-insulators (SOI), derive some performance advantage through the reduction of parasitic diffusion capacitance that would otherwise contribute to inefficient operation. However, these technologies have their own limitations. For example, there are many cost and material quality issues awaiting resolution before SOI can be a viable technology for commercial implementation. The channel mobility in SIMOX (oxygen-implanted silicon) or SOS (silicon-on-sapphire) SOI materials is not comparable to that of bulk or epitaxial silicon. Also, high defect density problems can arise from either the oxygen implantation or from a mismatch between lattice constants of silicon and the host crystal.
In U.S. Pat. No. 5,663,586 issued to Lin on Sep. 2, 1997, entitled, “FET DEVICE WITH DOUBLE SPACER,” the sub-threshold leakage current of a FET device is minimized by providing a polysilicon spacer on the vertical sidewalls of the device. First spacer elements of polysilicon are provided on the vertical sidewalls along with second spacer elements of SiO
2
over the first spacers. In contrast, the instant invention does not add spacer gates to the side of the first gate. Rather, the second gate set is built with a damascene process that uses the first gate as a mandrel.
In U.S. Pat. No. 5,606,187 issued to Bluzer et al., on Feb. 25, 1997, entitled, “CHARGE COUPLED DEVICE GATE STRUCTURE HAVING NARROW EFFECTIVE GAPS BETWEEN GATE ELECTRODES,” gaps between the transparent gates are filled with dielectric material having a predetermined (high) dielectric constant, thereby making the gap behave as if it were smaller than its actual physical size, and improving the device electrical behavior. Depending upon the dielectric, the junction parasitic capacitances may be effectively reduced. Importantly, the gaps between the gates are filled after gate definition.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a multigate MOSFET device structure having reduced parasitic capacitance.
It is another object of the present invention to provide a method of making a multigate MOSFET device having reduced parasitic capacitance.
A further object of the invention is to provide a multigate FET structure with reduced parasitic diffusion capacitance for low power applications.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
SUMMARY OF THE INVENTION
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a method of forming a multi-gate FET comprising: providing a substrate; forming a plurality of separated, insulated gates on the substrate, each of the gates having electrically insulating material on at least top, bottom and two opposing side surfaces of the gates; forming a dielectric layer on the substrate between the insulated gates; depositing a layer of electrically conductive material between the insulated gates; planarizing the layer of conductive material down to the insulating material on the top surface of the insulated gates to expose the insulating material and form at least one region of the conductive material defined by and between the insulating material on the gates; and implanting diffusion regions into the substrate adjacent to, and beneath a portion of, two distal ones of the plurality of insulated gates for defining therebetween in the substrate a channel region of the multi-gate FET that is controlled by the two distal ones of the insulated gates and conductive region between them. The method further comprises, after planarizing, etching the conductive material to a level below the insulating material on the top surfaces of the insulated gates.
Additionally, the substrate is provided with shallow trench isolation structures, and the gates are formed and the diffusion regions are implanted between the shallow trench isolation structures. Contacts are also formed, electrically connected to the two distal ones of the insulated gates and conductive region between them.
The method further includes forming spacers adjacent the distal side surfaces of the two distal ones of the insulated gates. The substrate provided may be a silicon-on-insulator (SOI) substrate.
In a second aspect, the instant invention is directed to a method of forming a multi-gate FET comprising: providing a substrate; forming a plurality of separated, insulated gates on the substrate, each of the gates having electrically insulating material on at least top, bottom and two opposing side surfaces of the gates; forming a dielectric layer on the substrate between the insulated gates; depositing a layer of electrically conductive material on and between the insulated gates; planarizing the layer of conductive material down to the insulating material on the top surface of the insulated gates to expose the insulating material and form at least one region of the conductive material defined by and between the insulating material on the gates; etching the conductive material to a level below the insulating material on the top surfaces of the insulated gates; implanting diffusion regions into the substrate adjacent to, and beneath a portion of, two distal ones of the plurality of insulated gates for defining therebetween in the substrate a channel region of the multi-gate FET that is controlled by the two distal ones of the insulated gates and conductive region between them; forming spacers adjacent the distal side surfaces of the two distal ones of the insulated gates; and, forming contacts electrically connected to the two distal ones of the insulated gates and conductive region between them.
In a third aspect, the instant invention is directed to a multi-gate FET comprising: a substrate; a plurality of separated, insulated gates on the substrate, each of the gates having electrically insulating material on at least top, bottom and two opposing side surfaces of the gates; a dielectric layer on the substrate between the insulated gates; a layer of electrically conductive material between the insulated gates forming at least one region of the conductive material defined by the insulating material on the gates; and, a layer of electrically conductive material between the insulated gates forming at least one region of the conductive material defined by and between the insulating material on the gates; and, diffusion regions in the substrate adjacent to, and beneath a portion of, two distal ones of the plurality of insulated gates defining therebetween in the substrate a channel region of the multi-gate FET controlled by the two distal ones of the insulated gates and conductive region between them.
In a fourth aspect, the instant invention is directed to a multi-gate FET comprising: providing a substrate; a plurality of separated, insulated gates on the substrate, each of the gates having electrically insulating material on at least top, bottom and two opposing side surfaces of the gates; a dielectric layer on the substrate between the insulated gates; a layer of electrically conductive material between the insulated gates forming at least one region of the conductive material defined by and between the insulating material on the gates; diffusion regions in the substrate
Adler Eric
Bernstein Kerry
Ellis-Monaghan John J.
Lary Jenifer E.
Nowak Edward J.
DeLio & Peterson LLC
Henkler Richard A.
International Business Machines - Corporation
Reynolds Kelly M.
Wojciechowicz Edward
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