Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
2001-03-30
2002-06-11
Chervinsky, Boris (Department: 2835)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C361S761000, C257S723000, C257S724000, C257S778000, C174S050510, C438S107000, C438S108000
Reexamination Certificate
active
06404648
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present disclosure relates to semiconductor devices and methods for constructing the same. More particularly, the invention relates to a multi-die integrated circuit (IC) assembly integrating multiple dies.
2. Discussion of the Related Art
Generally, the integrated circuit (IC) industry is continually attempting to improve the frequency of operation, performance, and integration density of integrated circuits (ICs) while simultaneously attempting to add new functionality and features to the same ICs. In order to improve performance while simultaneously increasing functionality, many different fabrication and packaging techniques are being utilized or proposed for use in the industry.
A number of different packaging technologies exist for attaching semiconductor devices to a printed circuit board (PCB). Three exemplary packaging technologies include ball-grid array (BGA), chip scale package (CSP), and direct chip attach (DCA). BGA is an older technology relative to CSP and DCA. A BGA consists of a plurality of solder balls spatially separated by a plurality of corresponding pads. The pads and their associated solder balls are distributed across an external surface of a BGA substrate such that when a suitably configured PCB comes in close contact with the plurality of solder balls, the solder balls contact the desired PCB interface conductors. The interface conductors located on the PCB are each configured with a similar pad spatially arranged to interface with a particular conductor on the BGA. In order to further interface with a semiconductor die such as a flip-chip die, a portion of the BGA may be configured with a plurality of contact pads suitably sized and arranged to interface with a plurality of solder bumps provided on a surface of the flip-chip. In this way, circuits contained on a flip-chip die may be interfaced with external circuits associated with the BGA. The various conductive elements of the BGA may further interface one or more circuits located on the flip-chip die with one or more circuits located on the PCB.
A CSP, on the other hand, is an interface assembly wherein a plurality of semiconductor dies interface conductors having associated pads for connecting a semiconductor die to a PCB are located on one surface of the semiconductor die. The remaining surfaces of the semiconductor die are typically encapsulated in a non-conducting material. The CSP interface architecture increases the utility of a given PCB surface area by decreasing the area required to attach the semiconductor die to the PCB. The last technology of the three exemplary construction technologies, DCA, involves the direct attachment of the semiconductor die to the PCB without a package. Flip-chips provided with solder bumps are representative of a DCA assembly.
As the demand for high speed, high performance, low cost, and portable semiconductor based electronic devices grows the integration density and complexity of semiconductor-packaging technologies continually adapts. One approach for achieving a greater integration density is to construct semiconductor device packages having multiple semiconductor dies. These packages are often referred to as multi-chip modules. Multi-chip modules (MCMs) may contain microprocessor circuits along with a host of peripheral circuits, such as memory management units, input/output controllers, peripheral component interconnect controllers, application specific integrated circuits and other such devices.
The most common MCM is a “side-by-side” MCM. In a “side-by-side” configuration, two or more dies are mounted next to each other on a mounting surface that may take the form of a plastic molded cavity, a cavity package, or a chip on board (COB) assembly. The die may be mounted directly to a principle-mounting surface or the die may be mounted on a substrate, which may be further mounted to a principle-mounting surface (e.g., a BGA or a PCB). Electrically conductive connections among the die and the various electrical leads are commonly made via wire bonding to a plurality of conductive pads associated with the dies.
An exemplary MCM configuration is illustrated in FIG.
1
. The multi-chip arrangement in the perspective schematic of
FIG. 1
is representative of the general configuration selected for the Pentium Pro™ product from Intel Corporation (Santa Clara, Calif.). As illustrated in
FIG. 1
, the MCM
10
comprises a first semiconductor device
12
a
and a second semiconductor device
12
b
. As shown in
FIG. 1
, the first and second semiconductors
12
a
and
12
b
may be arranged laterally adjacent to one another in the MCM
10
. The first semiconductor
12
a
and the second semiconductor
12
b
may both be configured with a plurality of bond pads
14
along one or more edges of the respective semiconductor devices
12
a
,
12
b
. These bond pads
14
may be used to electrically couple select conductors located on the respective semiconductor dies
12
a
,
12
b
to circuitry on one or more integrated circuits or other devices external to the MCM
10
.
One problem associated with placing multiple semiconductor dies within a single package is related to the distribution of the various signals, which traverse the various semiconductor dies. Many semiconductor dies can be the size of a postage stamp. At this scale, internal routing lengths on a single IC configured on either semiconductor device
12
a
,
12
b
may be significant and performance limiting. Once internal IC routing lengths are traversed across the surface of the IC, a bond pad
14
is needed to enable the circuit elements on the IC to interface with external circuits. As a result, the bond pads
14
and necessary wire length needed to traverse the gap from the first semiconductor device
12
a
to the second semiconductor device
12
b
further increase the routing length of interface signals. These relatively lengthy interface connections have increased resistance, inductance, and capacitance than most other conventional IC connections. Due to the change in the electrical characteristics (i.e., the characteristic impedance) between internal IC interconnections and the lengthy interface connections, many high-performance IC products (e.g., products having a desired operation at or above a few megahertz) may not meet timing specifications and may be frequency limited.
While the MCM module
10
illustrated in
FIG. 1
allows more integrated circuits to be packaged in a single semiconductor package, the MCM
10
still suffers from parasitic impedance and routing problems as previously described. Another disadvantage results from the fact that the overall MCM
10
contains a larger footprint thus requiring a larger surface area on a PCB configured to interface with the MCM
10
. As illustrated in the schematic diagram of
FIG. 1
, the first semiconductor
12
a
may be electrically interconnected with the second semiconductor
12
b
via one or more line bonds
20
that traverse the gap between adjacent lateral edges of the semiconductors
12
a
and
12
b
. In order to control input and output (I/O) interface-conductor impedance characteristics and to limit the physical size of circuit elements required to transmit various signals across dies, prior art “side-by-side” MCM approaches have generally resorted to placing high-speed interface drivers along adjacent edges of the sending and receiving semiconductor dies. The concentration of I/O drivers along adjacent edges of the various multiple dies in a “side-by-side” MCM limits the number of impedance controlled interfaces between the various dies. In addition, the concentration of high-speed interface signals in increasingly close quarters, increases the probability of encountering radio-frequency interference between interface conductors.
A second problem that adversely affects the manufacture of semiconductor ICs in general is that absent new manufacturing technology, requirements to increase the functionality available in various IC devices force IC designers to use larger and larger die areas
Harper Timothy V.
Slupe James P.
Chervinsky Boris
Hewlett-Packard Co.
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