Semiconductor memory device using double layered capping...

Details Semiconductor memory device using double layered capping... Semiconductor memory device using double layered capping...

2001-02-05

2002-06-11

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Junction field effect transistor

C257S306000

Reexamination Certificate

active

06403996

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of fabricating a semiconductor device and a semiconductor device fabricated thereby and, more particularly, to a method of forming a semiconductor memory device using a double layered capping pattern and a semiconductor memory device formed thereby.
BACKGROUND OF THE INVENTION
Attempts to increase device integration density in microelectronic integrated circuits typically result in the fabrication of devices of continually decreased size and increased density. In order to provide electrical access to these devices, conventional techniques to photolithographically define the location of contact holes to these devices have also had to improve. Such improvements have typically included the development of photolithographic alignment techniques having reduced tolerances. Reduction of contact hole size may not represent an acceptable approach when forming highly integrated devices because reductions in contact hole size typically lead to substantial and unacceptable increases in contact resistance. Techniques to reduce photolithographic alignment tolerances have typically not scaled at the same rate as techniques to scale the size of microelectronic devices. To address this limitation associated with photolithographic alignment, self-aligned contact hole fabrication techniques that are less dependent on photolithographic accuracy have been developed.
A method of forming self-aligned contact hole is disclosed in U.S. Pat. No. 5,763,323, entitled “Method for Fabricating Integrated Circuit Devices Including Etching Barrier Layers and Related Structures” by Kim et al., which is hereby incorporated herein by reference. According to U.S. Pat. No. 5,763,323, an insulating layer is formed on a substrate and a plurality of parallel conductive lines are formed on the insulating layer. An etch barrier is then formed on each of the parallel conductive lines and contact holes are formed between the etch barriers. The contact holes expose portions of the substrate without exposing the plurality of parallel conductive lines. In particular, the contact holes can be formed by forming a patterned mask layer on the insulating layer and etch barriers, and by etching the exposed portions of the insulating layer. The patterned mask layer selectively exposes a plurality of parallel strips orthogonal to the plurality of parallel conductive lines. Related structures are also disclosed.
In addition,
FIGS. 1A
to
5
A and
FIGS. 1B
to
5
B are cross-sectional views for illustrating a fabrication method of a semiconductor memory device according to conventional technology. Here,
FIGS. 1A
to
5
A are cross-sectional views taken along the line perpendicular to word lines of a DRAM device. Also,
FIGS. 1B
to
5
B are cross-sectional views taken along the line perpendicular to bit lines of a DRAM device. Referring to
FIGS. 1A and 1B
, an isolation layer
3
a
is formed on a predetermined region of a semiconductor substrate
1
to define an active region. A plurality of insulated word line patterns are formed on the substrate having the isolation layer
3
a
. The word line patterns cross over the active region and each of the word line patterns comprises a word line
7
and an insulating capping pattern
9
, which are sequentially stacked. A gate oxide layer
5
is interposed between the word line pattern and the substrate having the isolation layer
3
a
. Impurity regions
13
s
and
13
d
are formed at the active region. The impurity region
13
d
between the word line patterns operates as a common drain region of a cell transistor and the impurity region
13
s
opposite to the common drain region
13
d
operates as a source region of a cell transistor. A gate spacer
11
is formed on sidewalls of the word line patterns.
The resulting structure, including the gate spacer
11
is then covered with a conformal etch stop layer
15
such as a silicon nitride layer. After forming the etch stop layer
15
, a lower separating layer
17
is formed over an entire surface of the etch stop layer
15
. The lower separating layer
17
fills gap regions between the word line patterns. A first photoresist layer is formed on the lower separating layer
15
and is patterned to form a first photoresist pattern
19
defining pad contact holes.
Referring to
FIGS. 2A and 2B
, the lower separating layer
17
is etched using the first photoresist pattern
19
as a etch mask, to thereby expose a portion of the etch stop layer
15
. Subsequently, the exposed etch stop layer
15
is etched to form pad contact holes exposing the common drain region
13
d
and the source regions
13
s
. During this etching step, the upper corner regions of the word line patterns can be easily over-etched. Accordingly, deformed insulating capping patterns
9
a
having convex top surfaces remain on the word lines
7
as shown in FIG.
2
A. The narrower the width of the word line patterns, the sharper the remaining top surfaces thereof. In addition, the gate spacer
11
is likewise etched during the etching process for forming the pad contact holes. Thus, a deformed gate spacer
11
a
is formed. As a result, the thickness of the gate spacer
11
and the insulating capping patterns
9
covering the upper corner region of the word lines
7
is substantially reduced as shown in FIG.
2
A. In the meantime, the etching process for forming the pad contact holes results in the formation of a lower separating layer pattern
17
a
that isolates the adjacent pad contact holes from each other. After removing the first photoresist pattern
19
, a doped polysilicon layer
21
is formed on an entire surface of the substrate including the lower separating layer pattern
17
a
. The doped polysilicon layer
21
completely fills the pad contact holes.
Referring to
FIGS. 3A and 3B
, the doped polysilicon layer
21
is planarized using a chemical mechanical polishing (CMP) process until the deformed insulating capping patterns
9
a
are exposed, thereby forming bit line pads
21
d
and storage node pads
21
s
on the exposed common drain regions
13
d
and the exposed source regions
13
s
respectively. At this time, the deformed insulating capping patterns
9
a
become further etched. Thus, the word lines
7
can be easily exposed or very thin insulating capping patterns
9
a
′ may exist on the word line
7
as shown in FIG.
3
A. This is due to the convex top surfaces of the deformed insulating capping patterns
9
a
. That is to say, in the event that the top surface of the CMP stopper has a sharp profile, the polishing selectivity is reduced. Therefore, during the CMP process, the top surface of the CMP stopper should be flat in order to increase the polishing selectivity.
An inter-layer insulating layer
23
is then formed on an entire surface of the resultant structure including the bit line pads
21
d
and the storage node pads
21
s
. A plurality of bit line patterns are formed on the inter-layer insulating layer
23
. Each of the bit line patterns comprises a bit line
25
and an insulating capping pattern
27
which are sequentially stacked. The bit line patterns are formed so that they cross over the word line patterns. Additionally, the respective bit lines
25
are electrically connected to the bit line pads
21
d
via bit line contact holes (not shown). A bit line spacer
29
is formed on sidewalls of the bit line patterns. An upper separating layer
31
is then formed on an entire surface of the resultant structure, including the bit line patterns and the bit line spacer
29
.
Referring to
FIGS. 4A and 4B
, a second photoresist pattern
33
is formed on the upper separating layer
31
. The upper separating layer
31
and the inter-layer insulating layer
23
are sequentially etched using the second photoresist pattern
33
as a etch mask, thereby forming storage node plug contact holes
35
exposing the storage node pads
21
s
. At this time, even though the insulating capping patterns
27
and the bit line spacer
29
operate as etch stoppers, the insulating capping patterns
27
and t

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