Driving point model utilizing a realizable reduced order...

Details Driving point model utilizing a realizable reduced order... Driving point model utilizing a realizable reduced order...

2000-10-27

2002-12-17

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C703S002000

Reexamination Certificate

active

06496960

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to semiconductor design automation systems, and in particular to the simulation of integrated circuit designs of such systems. More specifically, the present invention relates to a driving point model utilizing a realizable reduced order circuit for determining a delay of a gate driving an interconnect having resistive, capacitive and inductive elements and a method of operation thereof.
2. Description of the Related Art
Development of a working integrated circuit chip is a process that involves creating a design specification, creating the logical design of the chip (typically in schematic form), validating the design, re-designing as necessary, fabricating the chip and testing the chip. Costs tend to be “end-loaded,” i.e., greater towards the end of the process than towards the beginning. The earlier in this process that a design error is detected, the earlier it can be corrected, saving a great deal of cost over a late-detected error. As a result, increasingly sophisticated steps are being taken to validate the design of a new chip, as early in the design process as possible.
Design validation requires thorough examination of the integrated circuit design and expected functional characteristics, taking into account a number of different factors, such as logical correctness of the design, timing factors (including net delay performance, effects of parasitic capacitances, etc.). Among these factors, net performance (specifically, net delay) is one of the most important. Many timing-related problems have been discovered in chips whose designs appear to be “logically” correct, at least on paper. This is because it is difficult for the designer to anticipate such delay contributors as wiring delays, i.e., net delays and the cumulative effects of distributed resistances, inductances and capacitances on the chips, especially from a post-layout point of view. The accuracy of delay determination affects not only the chip performance, but whether a chip meets its original design specification.
Virtually all integrated circuit designers today use semiconductor design automation systems which facilitate the capture, simulation, layout, and verification of integrated circuit designs. With the advance of semiconductor process technology, integrated circuits are becoming increasingly fast, and the once relatively small delays caused by interconnections, i.e., wiring, on a chip are becoming a more dominant factor in integrated circuit performance. As a result, the ability to accurately model and calculate delays is a crucial requirement for any semiconductor design automation system.
From any driving point to any receiving point on a net, there is an associated delay. This time is due to a complicated combination of parasitic capacitances, wiring resistances, wire lengths, etc. Some nets have multiple drivers, e.g., a number of open-drain or tri-state drivers, or loops, e.g., clock rings, making their (accurate) analysis particularly complicated. The delay for a net is determined by modeling the net and analyzing the delay according to the model. One of the most serious problems in delay calculation (determination) is that accurate models tend to complicate delay calculations, resulting in expensive delays in the design cycle while computation-intensive net delays are being calculated. As a result, most prior-art net delay calculation techniques compromise on the accuracy (faithfulness to reality) of the model of the net in order to decrease the amount of calculation time required. Unfortunately, in doing so most such techniques sacrifice enough accuracy that the results of delay calculation are only very rough approximations of actual chip performance. As a result, many chips, particularly those with complicated timing relationships between signals, have subtle timing-related problems when they are built. The designs of such chips must then be altered, re-simulated, etc., and a new chip must be fabricated. This process is extremely costly.
It has been well established that interconnect effects must be accounted for to ensure accurate static timing analysis. Traditionally, gate level static timing analyzers have broken down the path delay as the sum of the gate delay and the wire or interconnect delay. Since the interconnect is a linear circuit, model order reduction techniques based on moment matching have been employed to compute its delay efficiently. However, since gates are non-linear devices, two distinct approaches have been used for fast computation of gate delay. Firstly, the gate delay is precharacterized in terms of input transition time and output load capacitance using detailed circuit simulators such as SPICE and implemented using lookup-tables. Alternatively, the gate delay is obtained “on the fly” using fast timing simulators, see, e.g., A. Devgan and R. A. Rohrer “Adaptively Controlled Explicit Simulation,” IEEE Trans. On CAD, June 1994.
Regardless of the method used to compute gate delays, an accurate characterization of the loading due to the interconnect at the output of the gate must be made. While a simple approach would be to lump the total capacitance of the interconnect at the output of the gate, the resistive shielding renders such a model inaccurate. A more accurate model for RC interconnect, the so called pi-model, has been used in many timing analysis and physical design tools for modeling the driving point load. However, the pi-model can no longer be used if the inductive effects are significant; and with faster signal transition times, increasing die sizes, and the advent of newer materials such as copper, on-chip inductance can no longer be ignored.
Accordingly, what is needed in the art is an improved driving point model that mitigates the above-described limitations in the prior art. More particularly, what is needed in the art is a driving point model for interconnects having resistive, capacitive and inductive elements.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide an improved driving point model for interconnects having inductance.
It is another object of the invention to provide a method for determining an equivalent load at a gate driving an interconnect having resistive, capacitive and inductive elements.
It is another object of the invention to provide a method for determining a delay at a gate driving an interconnect having resistive, capacitive and inductive elements.
To achieve the foregoing objects, and in accordance with the invention as embodied and broadly described herein, a method for determining an equivalent load at the output of a gate driving an interconnect having resistive, inductive and capacitive elements is disclosed. The method includes modeling the interconnect utilizing a passive driving point model to derive a realizable reduced order circuit for the interconnect. In an advantageous embodiment, the realizable reduced order circuit includes a first resistance parallel-coupled to an inductance and series-coupled to a pi-model equivalent circuit, where the pi-model equivalent circuit includes a second resistance and first and second capacitances. In a related embodiment, the first four moments of an input admittance of the interconnect are obtained to model the interconnect, where the first four moments are characterized by:
z
−1
=1
/C,
z
0
=[(1
+k
)
2
R
2
]/4,
z
1
=L
−({fraction (1/16)})
C
(1
−k
)(1
+k
)
3
R
2
2
, and
z
2
=({fraction (1/64)})
C
2
(1
−k
)
2
(1
+k
)
4
R
2
3
−(
L
2
/R
1
),
wherein z
−1
, z
0
, z
1
, and z
2
are the first, second, third and fourth moments, respectively, L, R
1
and R
2
are the inductance, first and second resistances, respectively, k is a realizability parameter and the first and second capacitances are defined by (1−k)(C/2) and (1+k)(C/2), respectively. Next, the realizable reduced order circuit is utilized to determine the equivalent load that, in an advantageous embodiment, is

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