Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-07-09
2002-11-19
Tran, M. (Department: 2818)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06484303
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a layout designing apparatus, a layout designing method and a semiconductor device, and more particularly, to a layout designing apparatus outputting a layout pattern including a dummy pattern, a layout designing method, and a semiconductor device manufactured using the same.
2. Description of the Background Art
Conventionally, a photolithographic processing technology has been used for forming predetermined interconnections, electrodes and so forth in the process of manufacturing a semiconductor device. In the photolithographic processing technology, a resist film is formed on the surface of a semiconductor substrate, and thereafter transfers a pattern to be transferred (hereinafter referred to as “transfer pattern”) formed on a photomask onto this resist film by exposure and development processes.
Here, the resist film onto which the transfer pattern is transferred is formed on an interlayer insulating film or the like formed on the surface of the semiconductor substrate. A substructure such as interconnections or electrodes are generally formed under the interlayer insulating film. Because of such a substructure, an irregular portion may be formed on the upper surface of the interlayer insulating film. Existence of such an irregular portion forms a resist-film irregular portion corresponding to the irregular portion on the upper surface of the resist film formed on the interlayer insulating film. In a region where such a resist-film irregular portion is formed, the distance between the photomask and the upper surface of the resist film will be locally varied in the exposure step of transferring the transfer pattern of the photomask onto the resist film. This has caused problems such that the dimension of the transfer pattern transferred onto the resist film is varied, or that the transfer pattern is not resolved.
To prevent such problems from occurring, a step of planarizing the upper surface of the interlayer insulating film by the CMP (Chemical Mechanical Polishing) method is carried out before forming of the resist film. However, when the density of interconnections or the like in the substructure is not uniform and steps in the irregular portion on the upper surface of the interlayer insulating film are large, it was sometimes difficult to sufficiently planarize the upper surface of the interlayer insulating film by the CMP method.
Therefore, conventionally, a method has been employed in which dummy interconnections are formed in a region where no interconnection exists as the substructure to make the density of structures such as the interconnections uniform in the substructure in order to reduce the steps in the irregular portion (to increase the flatness) on the upper surface of the interlayer insulating film. To form such dummy interconnections, a layout designing method as described below is executed in a layout designing step in the manufacturing process of a semiconductor device.
FIG. 30
is a flow chart for illustrating a conventional layout designing method. Further,
FIG. 31
is a schematic view showing a layout pattern obtained by the layout designing method shown in FIG.
30
. Referring to
FIGS. 30 and 31
, the conventional layout designing method will be described.
Referring to
FIGS. 30 and 31
, in a dummy pattern arrangement method of the conventional layout designing method, first, the step of entering circuit patterns
101
a
to
101
c
such as interconnections constituting a circuit of the semiconductor device (S
110
) is executed. In this step of entering the circuit patterns (S
110
), data of the coordinates of circuit patterns
101
a
to
101
c
are entered and held in a memory of a computer system in which a software executing the layout designing method is installed.
Next, the step of producing dummy patterns
103
a
and
103
b
(S
130
) on the entire surface of a chip region in which circuit patterns
101
a
to
101
c
are arranged is executed. In the step of producing dummy patterns (S
130
), dummy patterns
103
a
and
103
b
are arranged in a matrix with a predetermined pitch. Further, the size of dummy patterns
103
a
and
103
b
are also predetermined. These dummy patterns
103
a
and
103
b
are the patterns for forming dummy interconnections.
Subsequently, the step of extracting dummy patterns
103
a
(S
140
), which are located in regions that are not overlapping with circuit patterns
101
a
to
101
c
and are spaced by predetermined distances from circuit patterns
101
a
to
101
c
, is executed.
Thereafter, the step of outputting a layout pattern (S
150
), including dummy patterns
103
a
extracted in the step of extracting the dummy patterns (S
140
) and circuit patterns
101
a
to
101
c
, is executed. Thus, the layout pattern can be obtained in which dummy patterns
103
a
indicated by the solid line are arranged in the regions where none of circuit patterns
101
a
to
101
c
is formed, as shown in FIG.
31
.
Then, the transfer pattern of a photomask is formed based on such a layout pattern. Moreover, interconnections and dummy interconnections are formed on the semiconductor substrate based on this transfer pattern by the photolithographic processing.
The above-described conventional layout designing method had a problem as described below. In the conventional layout designing method, values that were predetermined irrespective of circuit patterns
101
a
to
101
c
were used for the size and the pitch of dummy patterns
103
a
and
103
b
in the step of producing dummy patterns (S
130
). In such a case, the pitches with which circuit patterns
101
a
to
101
c
are formed and the pitch with which dummy patterns
103
a
and
103
b
are formed may be different. Thus, circuit patterns
101
a
to
101
c
and dummy patterns
103
a
and
103
b
would overlap with each other more than necessary as shown in
FIG. 31
, and hence the number of dummy patterns
103
b
not extracted in the step of extracting dummy patterns (S
140
) would be increased. As a result, there were some cases in the layout pattern obtained in the step of outputting the layout pattern (S
150
), such that dummy patterns were not arranged in portions with enough spaces for the dummy patterns to be arranged (e.g. the region between circuit pattern
101
b
and circuit pattern
101
c
), and the uniformity of the pattern density were insufficient.
As such, when the pattern density is not sufficiently made uniform, not enough dummy interconnections will be arranged around the interconnections in the structure of the semiconductor device formed based on this layout pattern. This results in formation of an irregular portion on the upper surface of the interlayer insulating film formed on the structure of such interconnections or the like, which was sometimes impossible to be planarized by the CMP method.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a layout designing apparatus and a layout designing method capable of improving uniformity of the pattern density of a layout pattern in which a dummy pattern is formed, and to provide a semiconductor device manufactured using the layout designing method.
A layout designing apparatus according to one aspect of the present invention includes an entry unit for entering a plurality of circuit patterns of a semiconductor device; a recognition unit for recognizing positional data of the entered plurality of circuit patterns; a dummy pattern arrangement unit for producing a dummy pattern group including a plurality of dummy patterns, each of the plurality of dummy patterns being arranged per repetitive distance determined based on the recognized positional data of the circuit patterns; an extraction unit for extracting a final dummy pattern including a dummy pattern located in a region other than a region overlapping with the circuit patterns, from the dummy pattern group; and an output unit for outputting a layout pattern including the extracted final dummy pattern and the circuit patterns.
A case is now considered w
McDermott & Will & Emery
Tran M.
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