Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2001-02-20
2002-08-27
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S197000, C438S407000, C438S586000, C438S592000, C438S652000
Reexamination Certificate
active
06440826
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of manufacturing high-density integrated semiconductor devices exhibiting nickel silicide extensions off of the source/drain regions for landing contacts.
BACKGROUND ART
Conventional semiconductor devices comprise a substrate and various electrically isolated regions, called active regions, in which individual circuit components, such as transistors comprising gates and source/drain regions, are formed and interconnected. In one interconnection scheme, source/drain regions and gates of neighboring transistors are connected to one another by local interconnections to form standard cells which, in turn, are connected to each other locally and globally by several patterned metal layers interleaved with insulating layers formed above and extending substantially horizontally with respect to the substrate surface. The metal layers are connected to one another and to the local interconnection by contacts landed on the active areas on which metal silicide layers have been formed.
Current demands for high density and performance associated with ultra large scale integration require feature designs of about 0.25 micron and under, increased transistor and circuit speeds and improved reliability. Meeting increased performance and reliability demands require device features, e.g., transistor source/drain regions and gate electrodes, to be manufactured with high precision and uniformity. Achieving precise and uniform manufacturing while reducing design features in order to accommodate increased density demands challenges the limitations of conventional contact and interconnection technology.
In order to form local interconnects involving transistors, the active regions, e.g., the source/drain regions, must be of a sufficient size to land the contacts on the desired area to form a junction while also placing the contact at a location relative to the gate electrode that falls within a predetermined tolerance distance required for the transistor to function properly. However, larger active areas have higher source/drain capacitance, which undesirably interferes with semiconductor performance.
Consequently, reducing the size of the source/drain region in order to achieve increased design density and to reduce source/drain capacity is limited using conventional technology by the area required to land the contacts to form local interconnects.
Additional challenges arise as device sizes decrease. For example, as gate electrode lengths are scaled down, the source and drain junctions and polycrystalline silicon line width must also be scaled down. However, scaling down the source and drain junctions and polycrystalline line width increases parasitic resistance in the source and drain diffusion layers and the gate electrode, and also increases the sheet and contact resistance of the gate electrode and source/drain regions.
Salicide technology comprises forming metal silicide layers on the source/drain regions and/or on the gate electrode of a semiconductor device in a self-aligned manner. Salicide technology reduces parasitic sheet and contact resistance in the source and drain diffusion layers and the gate electrode that results from scaling down the source and drain junctions and polycrystalline silicon line width.
Silicides are typically formed by reacting a metal with silicon (Si). This is accomplished by heating, e.g., rapid thermal annealing, the wafer to a reaction temperature for a period of time sufficient for the metal layer to react with underlying Si to form a metal silicide layer on the source/drain regions and the gate electrode.
Various metals react with Si to form a metal silicide, however, titanium (Ti) and cobalt (Co) are currently the most common metals used. Recently, attention has turned towards nickel (Ni) to form nickel silicide utilizing salicide technology because nickel silicide avoids many limitations associated with TiSi
2
and CoSi
2
. The formation of nickel silicide requires less Si than TiSi
2
and CoSi
2
. Nickel silicide also exhibits almost no linewidth dependence on sheet resistance. Nickel silicide is normally annealed in a one step process, vis-a-vis a process requiring an anneal, an etch, and a second anneal, as occurs in TiSi
2
and CoSi
2
saliciding. In addition, nickel silicide exhibits lower film stress, i.e., causes less wafer distortion, than conventional Ti or Co silicides.
Although the use of Ni in salicide technology has certain advantages over using Ti or Co, there are problems associated with Ni. Metal silicide resistivity and, thus, semiconductor device performance, varies based on whether the silicide is metal-rich. Low resistivity is the preferred phase for metal silicides, including nickel silicide, as it improves device performance in the areas of switching speed and source to drain drive current. The transformation to a low resistivity nickel silicide, e.g, NiSi, is affected by the temperature at which annealing occurs. In order to form NiSi, annealing typically must occur at 400° C. or greater. However, at these temperatures, the annealing causes nickel suicide to creep out of the active regions.
There exists a need to reduce the size of the active areas in order to achieve improved design density while enabling the formation of the desired contact junction and the landing of contacts at the proper tolerance distance from the gate electrode.
DISCLOSURE OF THE INVENTION
The above-mentioned needs and other needs are met by embodiments of the present invention, which provide a method of manufacturing high-density integrated semiconductor devices exhibiting nickel silicide extensions off of the source/drain regions for landing contacts, the method comprising forming a silicon substrate, forming a gate dielectric layer on the silicon substrate, and a gate electrode on the gate dielectric layer, forming sidewall spacers adjacent to the side surfaces of the gate electrode, forming source/drain regions, applying a mask with openings over field oxide areas in the silicon substrate adjacent to the outside edges of the source/drain regions, implanting Si into the exposed portions of the field oxide areas, depositing nickel over the wafer, heating the wafer to react the nickel with Si from the gate electrode, source/drain regions and Si-implanted field oxide areas to form a nickel silicide layer on the gate electrode, nickel silicide layers on the source/drain regions and nickel silicide extensions on the field oxide areas implanted with Si, removing unreacted nickel from the wafer, and landing contacts on the nickel silicide extensions at tolerance distances between the contact and the gate electrode and the contact and the end of the nickel silicide extension. In an embodiment of the present invention, the nickel silicide is NiSi.
An advantage of the present invention is the ability to improve design density by reducing the size of the active areas. The present invention enables the reduction of the active regions by landing contacts, in whole or in part, on the nickel silicide extensions, while maintaining the tolerance distances between the contact and the gate electrode and the contact and the end of the nickel silicide extension.
Reducing the active region size further improves semiconductor performance by lowering source/drain capacitance.
A further aspect of the present invention relates to a semiconductor device that includes a silicon substrate, polysilicon gate electrode, sidewall spacers, source/drain regions, and nickel silicide extensions on which contacts are landed in accordance with tolerance distances between the contact and the gate electrode and the contact and the end of the nickel silicide extension. The nickel silicide extensions are formed by applying a mask with openings over field oxide areas in the silicon substrate adjacent to the outside edges of the source/drain regions, implanting Si into the exposed portions of the field oxide areas, depositing nickel over the wafer, heating the wafer to react the nickel with Si from the gate electrode, source/drain regions a
Chaudhari Chandra
Chen Jack
LandOfFree
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