Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2001-05-04
2002-08-27
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S200000, C438S585000, C438S591000
Reexamination Certificate
active
06440783
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a thin film transistor display.
2. Description of the Prior Art
In a thin film transistor display, especially referring to a thin film transistor liquid crystal display (TFT-LCD), a lot of thin film transistors are arranged in a matrix as switches for driving liquid crystal molecules to produce brilliant images after co-operating with other elements such as capacitors and bonding pads. The advantages of the TFT-LCD include the portability, low power consumption, and low radiation. Therefore, the TFT-LCD is widely used in various portable products, such as notebooks, personal data assistants (PDA), etc. Moreover, the TFT-LCD replaces the CRT monitor in desktop computers gradually.
Please refer to
FIG. 1A
to FIG.
1
E.
FIG. 1A
to
FIG. 1E
are schematic diagrams of a prior art method for fabricating a thin film transistor display
10
, such as a thin film transistor liquid crystal display (TFT-LCD)
10
. The TFT-LCD
10
is formed on the surface of a substrate
12
. The surface of the substrate
12
comprises a transistor area
14
for forming a transistor
20
.
As shown in
FIG. 1A
, in the process of forming the TFT-LCD
10
, a metal layer (not shown) is deposited on the surface of the substrate
12
followed by the patterning of the metal layer to form a gate electrode
26
in the transistor area
14
. Subsequently, as shown in
FIG. 1B
, an insulating layer
28
, an amorphous silicon layer
30
, and a doped silicon layer
32
are formed on the substrate
12
, respectively. As shown in
FIG. 1C
, the doped silicon layer
32
, the amorphous silicon layer
30
, and the insulating layer
28
outside of the transistor area
14
are removed. As shown in
FIG. 1D
, an indium tin oxide (ITO) layer
36
is deposited on the surface of the substrate
12
. Then, as shown in
1
E, the pattern of the ITO layer
36
is formed, and a part of the doped silicon layer
32
in the transistor area
14
is removed to form a source electrode
38
and a drain electrode
40
.
The prior art method mentioned above needs only three masks to save the fabricating time. However, in order to reduce the manufacturing time, the ITO layer
36
with a high resistance is used to replace the metal layer as the electrical connecting lines. Consequently, the driving voltage of the display is increased, and the method is hard to apply to fabricate the display with large area.
Besides, in order to satisfy the dynamic images and multimedia applications, the thin film transistor display of the future must be brighter, have a high response rate, and a wide viewing angle. So, it is necessary to increase production yields and reduce costs by improving the materials or the fabricating processes of the display.
SUMMARY OF THE INVENTION
It is therefor an objective of the present invention to provide a method for fabricating a thin film transistor (TFT) display. The method is used to decrease the number of the mask, and reduce the resistance of the electrical elements in the display as well. The method can be applied to manufacture an in-plan switch (IPS) type TFT liquid crystal display.
In a preferred embodiment, the present invention provides a method for fabricating a thin film transistor display. The thin film transistor display is formed on a substrate. A first region and a second region are defined on the substrate. The first region includes a transistor area and the second region includes a pad area. A first metal layer is deposited and patterned on the substrate to form a gate electrode in the transistor area and a pad electrode in the pad area. An insulating layer and a semiconductor layer are deposited on the substrate, and an etching stopper is formed and patterned above the semiconductor layer. Then, a doped silicon layer is deposited on the semiconductor layer and the etching stopper. An opening area is defined in the pad area. Moreover, removing the insulating layer, the semiconductor layer, and the doped silicon layer positioned (a) outside the transistor area of the first region and (b) outside the pad area (c) within the opening area of the second region. The substrate is then exposed in the regions outside the transistor area and the pad area. An opening is formed in the pad area to expose the pad electrode. Further, a second metal layer is formed to cover the transistor area and the pad area, and the second metal in the opening is electrically connected to the pad electrode. The second metal layer is patterned. A channel area is defined in the transistor area, and then removing the second metal layer positioned (a) in the channel area of the first region, (b) outside a first side area of the first region, and (c) in the second region except the pad area. The doped silicon layer is then patterned to form a source electrode and a drain electrode in the transistor area by utilizing the left second metal layer as a mask. The source and drain electrodes are separated by the channel area. Therefore, the substrate will be exposed in the first side area of the first region and exposed in the second region except the pad area.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.
REFERENCES:
patent: 5756372 (1998-05-01), Wakui et al.
patent: 6207480 (2002-03-01), Cha et al.
patent: 2002/0038893 (2002-04-01), Wong
patent: 2002/0048866 (2002-04-01), Wong
AU Optronics Corp.
Booth Richard
Hsu Winston
Simkovic Viktor
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