Method of and apparatus for generating variable time delay

Details Method of and apparatus for generating variable time delay Method of and apparatus for generating variable time delay

1987-12-23

1990-10-02

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

With shift register

365 75, 365 76, 365240, G11C 700

Patent

active

049611690

ABSTRACT:
A variable length shift register comprises a memory cell array (1) having memory cells arranged in a matrix of row and columns, a variable length ring pointer (2) responsive to a bit length selecting signal for sequentially activating a single row in the memory cell array in a recirculated manner within a predetermined constant range, an input buffer (4) for writing data into a memory cell of the activated row, and an output buffer (5) for reading out data from a memory cell of the activated row.

REFERENCES:
patent: 3930239 (1975-12-01), Salters et al.
patent: 4429375 (1984-01-01), Kobayashi et al.
patent: 4890261 (1989-12-01), Hidaka et al.
Technical News: "MSM6901AS Variable Length Shift Register", Oki Electric Industry Co., Ltd., S83-07.
"Schieberegisterlange Elektrisch einstellbar zwischen 2 und 257 Bit".

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