Low phase jitter clock signal generation circuit

Details Low phase jitter clock signal generation circuit Low phase jitter clock signal generation circuit

1999-06-07

2002-08-13

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C710S058000, C713S501000, C713S503000, C327S115000

Reexamination Certificate

active

06434707

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to direct digital synthesis (DDS) clock signal generation, and more specifically, to a low phase jitter DDS clock signal generator.
BACKGROUND OF THE INVENTION
There is a demand in the electronics industry for DDS digital clock signal generators that have low phase jitter, high frequency resolution, and accuracy. The existing DDS technology that can produce digital clock signals having low phase jitter and high frequency resolution come at the expense of high power requirements and the use of expensive components.
To generate the desired clock signal, a clock generation circuit typically requires the use of a power consuming sine look-up table, an expensive digital to analog converter and an expensive low pass filter. A digital clock signal generation circuit typically uses a digital numerically controlled oscillator (NCO) to generate the desired clock signal with the multi-bit digital output of the NCO being fed to a sine look-up table. The output of the look-up table is then converted using a digital-to-analog converter (D/A). The analog signal is then passed through a low pass filter to remove frequencies associated with the input clock and aliasing effects. To generate a digital clock signal, the filtered sine wave is sliced to generate the desired clock signal.
U.S. Pat. No. 5,521,534 to Elliott discloses an example of a digital clock generator that uses a power consuming sine look-up table to produce digital clock signals. In Elliott, an NCO is used with a difference engine, a phase adder and a phase accumulator to create an output signal that is fraction of a clock reference signal. This output signal is then fed to a sine look-up table to generate a digital sine wave output signal having low phase jitter.
Other circuits, such as disclosed by U.S. Pat. No. 5,459,418 to Uriya et al., are able to generate a digital clock signal without using a power consuming sine look-up table. However, Uriya still requires the use of an expensive digital-to-analog converter. To generate the desired sine wave, Uriya uses a three sawtooth wave signal generation circuit. However, the generated sine wave requires shaping which Uriya accomplishes by using a counter and a digital-to-analog converter to affect rising and falling of the sine wave. The digital-to-analog converter is used to convert the contents of the counter to an analog value which is then applied to the three sawtooth wave signal generation circuit to shape the sine wave.
Therefore, there is a need to produce a digital clock signal having low phase jitter without requiring expensive and power consuming sine look-up tables, filters, or digital-to-analog converters.


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Dr. Neil Downie, Maran & Company Ltd. 1999 Technology Bulletin, “The Anti-Jitter Circuit” pp. 1-7.

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