Semiconductor memory device including sense amplifier...

Details Semiconductor memory device including sense amplifier... Semiconductor memory device including sense amplifier...

2001-01-24

2002-02-26

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S189050, C365S195000, C365S196000, C365S220000, C365S230060

Reexamination Certificate

active

06351423

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, and particularly to a semiconductor memory device including a latch type (cross-coupled type) sense amplifier circuit for sensing and amplifying the potential of a bit line pair. More particularly, the present invention relates to the structure of circuitry that drives a latch type sense amplifier.
2. Description of the Background Art
FIG. 1
shows a structure of a main part of a conventional semiconductor memory device disclosed in, for example, Japanese Patent Laying-Open No. 8-87887. Referring to
FIG. 1
, the semiconductor memory device includes two memory cell arrays ma
1
and mar with a plurality of memory cells mc arranged in a matrix therein. A bit line bl is arranged corresponding to each column of memory cells mc. A word line wl is arranged corresponding to each row of memory cells mc. In
FIG. 1
, bit lines bl
0
and bl
1
in memory cell array ma
1
and bit lines/bl
0
and /bl
1
in memory cell array mar are shown. The semiconductor memory device employs the open bit line configuration. A memory cell is arranged corresponding to the crossing of a bit line and a word line in each of memory cell arrays ma
1
and mar. A plurality of memory cells mc are coupled to a corresponding bit line in a unit of a predetermined number of memory cells. In other words, a memory unit has a NAND type memory cell structure.
The semiconductor memory device further includes a select gate
5
a
connecting bit line bl
0
or bl
1
to a common bit line bl according to select signals st
0
and st
1
, a select gate
5
b
connecting bit line /bl
0
or /bl
1
to a common bit line /bl according to select signals st
0
and st
1
, an equalize circuit
6
c
equalizing common bit lines /bl and bl to an intermediate voltage level when active, a temporary storage register
7
to store the data on common bit lines bl and /bl temporarily, and a cross-coupled sense amplifier sa sensing, amplifying, and latching the signal potentials of common bit lines bl and /bl when made active. Cross-coupled sense amplifier sa includes p channel MOS transistors (insulated gate type field effect transistor) having the gates and drains cross-coupled, and n channel MOS transistors having the gates and drains cross-coupled. Common bit lines bl and /bl are coupled to internal data lines db and /db via a column select gate
8
that is rendered conductive according to a column select signal cs
1
.
One sense amplifier sa is provided per two bit line pairs of each of memory cell arrays ma
1
and mar. Sense amplifier control circuit
1
is provided to drive a plurality of sense amplifiers sa in common.
Sense amplifier control circuit
1
includes a sense amplifier drive transistor
1
a
receiving a sense amplifier activation signal BSEP at its gate via an inverter
1
b
to be rendered conductive, for driving a sense amplifier drive signal BSAN on a sense amplifier drive line
4
n
to the level of a ground voltage, a sense amplifier drive transistor
1
c
rendered conductive when sense amplifier activation signal BSEP is active to drive a sense amplifier drive signal SAP on sense amplifier drive line
4
p
to the level of a power supply voltage VCC, an inverter
2
a
inverting sense amplifier activation signal BSEP, a NAND circuit
2
b
receiving an output signal of inverter
2
a
and a restore mode designating signal BRSTR, a sense amplifier drive transistor
3
a
receiving an output signal of NAND circuit
2
b
at its gate via an inverter
3
b
to be rendered conductive for driving sense amplifier drive line
4
n
to the level of the ground voltage, and a sense amplifier drive transistor
3
c
rendered conductive when output signal RBSEP of NAND gate
2
b
is at an L level to drive sense amplifier drive line
4
p
to the level of power supply voltage Vcc. Restore mode designating signal BRSTR specifies a mode of writing the data sensed and amplified by sense amplifier sa into the original memory cell.
The operation of the semiconductor memory device of
FIG. 1
will be described with reference to a waveform diagram of FIG.
2
.
One of memory cell arrays ma
1
and mar has a word line driven to a selected state. The word lines are at a nonselected state in the other memory cell array. The memory unit includes four memory cells. Here, the selected memory unit has the data read out from the memory cell located closest to common bit line bl or /bl. More specifically, word lines wl
0
, wl
1
, wl
2
and wl
3
are sequentially selected when memory cell array ma
1
is selected, as shown in FIG.
2
. Upon selection of word line wl
0
, select signals st
0
and st
1
are driven to an active state alternately, whereby bit lines bl
0
and bl
1
are connected to common bit line bl alternately. Similarly, bit lines /bl
0
and /bl
1
are sequentially coupled to common bit line /bl.
When select signals st
0
and st
1
attain an inactive state, activation of sense amplifier sa is carried out. More specifically, sense amplifier activation signal BSEP attains an active state of an L level (logical low) in a read out mode. At this stage, restore mode designating signal BRSTR maintains an H level (logical high). Since inverter
2
a
and NAND circuit
2
b
operate as a buffer circuit, sense amplifier drive transistors
1
a
,
1
c
,
3
a
and
3
c
conduct, whereby sense amplifier drive signal SAP is driven to the level of power supply voltage Vcc and sense amplifier drive signal BSAN is driven to the level of ground voltage. In response, sense amplifier sa is rendered active. A small signal voltage transferred from bit line bl
0
is sensed, amplified, and latched. The data sensed and amplified by sense amplifier sa is stored in temporary storage register
7
. The operation of driving the sense amplifier and storing the data into temporary storage register
7
following activation of select signals st
0
and st
1
is also carried out for other word lines wl
0
-wl
3
. By activating sense amplifier sa only common bit lines bl and /bl coupled to sense amplifier sa when select signals st
0
and st
1
are rendered inactive, the load on sense amplifier sa is reduced to allow a high speed sensing operation.
Upon completion of reading out the data of memory cells on word lines wl
0
-wl
3
, a restore mode operation of rewriting the data into the original memory cells is carried out. In the restore mode operation, restore mode designating signal BRSTR attains an L level, and control signal RBSEP is fixed at an H level. Therefore, sense amplifier drive transistors
3
a
and
3
c
maintain the inactive state. Data are rewritten into memory cells in the sequence opposite to that of reading out data. The data stored in temporary storage register
7
is amplified by sense amplifier sa. The amplified data is written into the original memory cell through select gate
5
a
. Sense amplifier drive lines
4
p
and
4
n
are only driven by sense amplifier drive transistors
1
c
and
1
a
, and drivability therefor is smaller than that in data read out. After sense amplifier sa is rendered active, in response to sense amplifier activation signal BSEP, to change the voltage level of common bit lines bl and /bl, select signal st
0
or st
1
is driven, and the bit line is driven gently by the sense amplifier via select gate
5
a
. By reducing the drivability of sense amplifier sa in the rewrite (restore) operation mode, leakage current Icc during rewriting can be reduced. Generation of power supply noise can be suppressed and reduction in current consumption is realized.
The restore operation to memory cell mc is carried out by repeatedly rendering sense amplifier activation signal BSEP active/inactive a predetermined number of times according to a clock signal CKB. Upon completion of rewriting data into memory cell mc connected to word line wl
3
, rewriting data into memory cell mc connected to word line wl
2
is then carried out. The rewriting operation into the memory cells connected to word lines wl
1
and wl
0
is sequentially carried out thereafter.
Clock

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