Method of fabricating dual damascene structure using a hard...

Details Method of fabricating dual damascene structure using a hard... Method of fabricating dual damascene structure using a hard...

1998-05-06

2002-02-26

Nguyen, Ha Tran (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S633000, C438S648000, C438S671000, C438S672000, C438S685000, C438S692000, C438S734000, C438S740000

Reexamination Certificate

active

06350682

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority benefit of Taiwan application Serial no. 87100935, filed Jan. 23, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method of fabricating dual damascene structure, and more particularly to a method of fabricating dual damascene structure which can improve the reliability of devices.
2. Description of the Related Art
FIGS. 1A-1D
is a cross sectional view of the conventional method of fabricating dual damascene structure. Referring to
FIG. 1A
, a substrate
100
having devices (not shown) is provided, and a defined conductive layer
102
, is formed on the substrate
100
. An oxide layer
104
and a silicon nitride layer
106
are deposited respectively on the substrate
100
. Referring to
FIG. 1B
, the silicon nitride layer
106
is patterned by photolithography and an opening is then formed. An insulating layer
108
is formed on the substrate
100
. The pattern of photoresist
110
anisotropically is used to define the insulating layer
108
by dry etching. When the insulating layer
108
is etched, using the silicon nitride layer
106
a
as a masking layer, and the oxide layer
104
which isn't covered by the silicon nitride layer
106
a
is etched until the conductive layer
102
is exposed. A trench
112
, as shown in
FIG. 1C
, is then formed within the insulating layer
108
a
and the oxide layer
104
a.
A metal layer
114
is formed on the insulating layer
108
a
and the trench
112
is filled with the metal layer
114
. The metal layer
114
is then planarized by chemical mechanical polishing (CMP) so a structure of the trench
114
filled up with metal layer
114
as shown in
FIG. 1D
is formed.
In the prior art as described above, the silicon nitride layer
106
is used to form on the oxide layer
104
. The silicon nitride layer
106
is used as not only a barrier layer but also a masking layer for etching. Because the material characteristics of the silicon nitride layer
106
, electrons can be easily trapped at the interface of the silicon nitride layer
106
and the oxide layer
104
, and a semi-conduction layer is formed at the interface. When voltage is applied on the wiring lines, the semi-conduction layer induces crosstalk or short circuit and the reliability of devices decreases.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a method of fabricating dual damascene structure without the formation of the silicon nitride layer. The occurrence of leakage current, crosstalk or short circuit between metal layers can be prevented. The device reliability can be improved and the process can be simplified.
To achieve these objects and advantages, and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention is directed towards a method of fabricating dual damascene structure. A substrate having devices and a defined conductive layer is provided. A dielectric layer and a hard mask material layer are formed respectively over the substrate. An opening is defined within the hard mask material layer. Because of the different selectivity of the hard mask material layer and the dielectric layer, a trench is formed within the dielectric layer by defining the hard material mask layer and a portion of dielectric layer until the conductive layer is exposed. The cross shape of the trench has a wider opening and a narrower bottom. A metal layer is then formed and the trench is filled up with the metal layer. The process of dual damascene structure is accomplished.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 5635423 (1997-06-01), Huang et al.
patent: 5663101 (1997-09-01), Cronin
patent: 5736457 (1998-04-01), Zhao
patent: 5801094 (1998-09-01), Yew et al.
patent: 5821169 (1998-10-01), Nguyen et al.
patent: 6077769 (2000-06-01), Huang et al.

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