Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2001-06-19
2002-11-12
Chaudhuri, Olik (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S655000, C438S656000, C438S657000, C438S738000
Reexamination Certificate
active
06479373
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method of producing doped polysilicon layers and polysilicon layered structures and a method of structuring such layers and layered structures which comprise polysilicon layers. The invention also relates to wafers and semiconductor chips which are fabricated using the methods specified above.
In particular, the invention relates to the fabrication of gate electrodes of transistors and of word lines in microelectronic components. The methods which are usually used for this comprise the successive deposition of four layers, namely gateoxide (SiO
2
), polycrystalline silicon (generally referred to in short as polysilicon), metal and/or metal silicide and a barrier layer (for example SiO
2
).
In order to ensure the necessary conductivity, the polysilicon layer is usually doped with doping atoms at high concentrations. In this process, a uniform distribution of the doping atoms over the polysilicon layer is very important. Otherwise, the adhesion of a doped polysilicon layer and adjacent metal (silicide) layer is not sufficient and the highly-doped polysilicon can only be structured with extreme difficulty when the doping level highly fluctuates.
In a particularly frequently used method, the procedure adopted in the context of such layered structures is such that it is only after the structuring of the layered structure by means of an etching procedure that the doping of the polysilicon layer is carried out. The doping atoms are thereby injected into the polysilicon from the adjacent metal silicide layer by heat treatment. It is virtually impossible to achieve uniform distribution of the doping atoms in this way. Another possibility is to add the doping compound to the process gas during the chemical vapor deposition and to deposit the doping atoms together with the silicon. In this way, a more uniform distribution of the doping atoms is attained, but the surface quality and adhesion to adjacent layers is not optimal with the conventional way of carrying out this method.
The adhesion problems between the layers can be eliminated to a certain extent by means of additional cleaning steps before the neighboring layer is applied. Such cleaning steps are however time-consuming and make the fabrication of the semiconductor components more expensive. The quality of the boundary layer (for example changes as a result of oxidization in air) also plays a decisive role in the electrical characteristics.
Difficulties arise with the structuring of the layers owing to different material properties of the individual layers on the one hand, and to concentration fluctuations within a layer on the other hand. It would be desirable to have straight-etched edges over all the layers with the lowest possible degree of damage to the gate oxide as a result of the etching process over the entire surface of the wafer, in order to ensure satisfactory quality of the micro-electronic components. The prior art methods do not fulfill these requirements to a satisfactory degree. On the one hand, the layer thicknesses have to be relatively great owing to the low selectivity of the known etching methods, in order to avoid undercutting of the layers and damage to the gate oxide. For this reason, it is virtually impossible to realize very flat layered structures. The homogeneity of the etching procedure over the area to be etched and the structure of the etched edges are not completely satisfactory either.
Precise structuring of a layered structure requires not only uniform quality of the individual layers within the structure but also a structuring method which runs over a plurality of steps which are selectively adapted to the material properties of the layered structure.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method of producing doped layers which are mainly composed of polycrystalline silicon which is deposited in a chemical vapor deposition, and for fabricating layered structures which comprise such a doped layer composed of polycrystalline silicon, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and in which the doping material is distributed homogeneously over the entire deposited area and the surface quality and adhesion to an adjacent layer is optimized. It is a further object to provide for processing which is simple and cost-effective and which may be carried out with conventional method steps and devices.
It is again a further object of the invention to provide a method by means of which layered structures which comprise at least one polysilicon layer and in particular one doped polysilicon layer and a metal layer or metal silicide layer can be structured with the highest possible degree of selectivity and homogeneity over the area to be structured, forming etched edges which are as straight as possible over all the etched layers. The selectivity should be high enough to permit the thickness of the layers in the layered structure to be reduced, and thus to permit flat microelectronic components to be fabricated.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method of producing a doped layer primarily composed of polycrystalline silicon, and a method of producing layered structures which include such a doped layer. The method comprises:
forming a polycrystalline silicon layer on a substrate by chemical vapor deposition and doping the layer by adding a doping compound to a process gas during the chemical vapor deposition; and
doping only during a determined deposition period in the forming step and terminating a feed of the doping compound to the process gas while continuing the chemical vapor deposition and forming a layer of substantially undoped silicon as a boundary layer of the doped polysilicon layer.
The novel process makes it possible to fabricate uniformly doped polysilicon layers which can be structured much more easily and better than polysilicon doped in a conventional way. Also, the surface quality and adhesion to an adjacent layer is improved.
With the above objects in view there is also provided a method of structuring a layered structure formed of at least one metal layer or metal silicide layer disposed on a poly-crystalline silicon layer, which comprises a three-step process including:
etching with fluorine-containing gas in a first step;
etching with a chlorine-containing gas in a second step; and
etching with a bromine-containing gas in a third step.
Particularly good results can be achieved if both methods are combined with one another to fabricate wafers and semiconductor chips.
Therefore, the invention also relates to wafers and semi-conductor chips produced with one or both methods according to the invention. They are defined as a semiconductor structure, comprising:
a substrate;
a doped polysilicon layer deposited on the substrate and doped in a chemical vapor deposition process;
a substantially undoped boundary layer contiguously formed on the doped polysilicon layer in the chemical vapor deposition process.
In accordance with another mode of the invention, the etching steps comprise etching the metal or metal silicide layer disposed on a boundary layer of substantially undoped silicon disposed on a doped polysilicon layer.
In accordance with an added feature of the invention, the doped polysilicon layer is formed directly on a gate oxide layer.
The doped layers referred to herein are composed mainly of polycrystalline silicon deposited by means of chemical vapor deposition (CVD). These layers are referred to herein in short as doped polysilicon layers for the sake of simplicity.
According to the invention, the layer is doped during its formation by adding the doping compound as a process gas during the chemical vapor deposition of the polycrystalline silicon. In other words, the doping takes place simultaneously with the deposition of the polycrystalline silicon. Compared with the implantation method, special steps for cleaning the polycrys
Drescher Dirk
Dreybrodt Joerg
Wege Stephan
Zedlitz Ralf
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Smoot Stephen W.
Stemer Werner H.
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