Semiconductor device having gate to body connection

Details Semiconductor device having gate to body connection Semiconductor device having gate to body connection

2001-01-08

2002-08-06

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S347000

Reexamination Certificate

active

06429487

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure of a semiconductor device, and more particularly to a structure of a DTMOSFET (Dynamic Threshold Metal Oxide Silicon Field Effect Transistor) formed on an SOI (Silicon On Insulator) substrate.
2. Description of the Background Art
A semiconductor device used for a portable device such as a notebook computer and a portable terminal is operated by a battery loaded in the portable device. Therefore, a portable device using a semiconductor device with less power consumption can be used for longer time with one charge of the battery. For this reason, it is desirable that a semiconductor device with less power consumption should be used in the portable device.
To reduce the power consumption of the semiconductor device, it is effective to reduce a power-supply voltage. For the power consumption of a CMOS digital circuit, for example, is in proportion to the square of the power-supply voltage. Since a drain current decreases when the power-supply voltage becomes three times as high as the threshold voltage or lower, the operating speed of the circuit largely decreases. Therefore, when the power-supply voltage is reduced, it is necessary to reduce the threshold voltage at the same time. A leak current flowing in a MOSFET when it is in an off state (when a gate-source voltage becomes the threshold voltage or lower), i.e., an off current, however, increases as the threshold voltage decreases. For this reason, when the threshold voltage is merely reduced, the power consumption in an off state increases. Further, a MOSFET used in a dynamic circuit, a memory cell array and the like sometimes causes malfunction when the threshold voltage is reduced.
Therefore, to reduce the power consumption of the semiconductor device without reducing the operating speed of the circuit, it is convenient that the threshold voltage can be set high in an off state and low in an on state, and as a structure to achieve this, a DTMOSFET is proposed (see U.S. Pat. No. 5,559,368).
FIG. 48
is a schematic diagram showing a structure of a DTMOSFET in the background art. An SOI substrate
101
has a multilayered structure in which a silicon substrate
102
, a BOX (Buried OXide) layer
103
and a silicon layer
104
are layered in this order. The SOI substrate
101
can be formed by a well-known method such as the SIMOX (Separation by IMplanted OXygen) and the BESOI (Bonded and Etchback SOI).
In the silicon layer
104
formed are an n
+
-type source region
156
and an n
+
-type drain region
157
which are paired with a body region (channel region)
115
sandwiched therebetween. On the body region
115
, a gate electrode
109
is formed with a gate oxide film
105
interposed therebetween. The gate electrode
109
has a multilayered structure in which a doped polysilicon layer
106
, a metal nitride layer
107
and a metal layer
108
are layered on the gate oxide film
105
in this order. The characteristic feature of the DTMOSFET lies in electrical connection between the gate electrode
109
and the body region
115
. A ground voltage is applied to the source region
156
and a power supply
158
such as a battery is connected to the drain region
157
.
FIG. 49
is a plan view schematically showing the structure of the DTMOSFET in the background art.
FIG. 50
is a cross section showing a cross-sectional structure taken along the line X
100
of FIG.
49
. Referring to
FIG. 50
, an STI (Shallow Trench Isolation)
117
is formed in the silicon layer
104
in the isolation region of the SOI substrate
101
. A bottom surface of the STI
117
is in contact with an upper surface of the BOX layer
103
.
In an element formation region of the SOI substrate
101
defined by the STI
117
, a p
+
-type impurity diffusion region
111
adjacent to the STI
117
and the body region
115
adjacent to the impurity diffusion region
111
are formed in the silicon layer
104
. On the body region
115
, the gate oxide film
105
and the gate electrode
109
are formed and on the gate electrode
109
, an interlayer insulating film
112
is formed.
On the impurity diffusion region
111
, a metal plug
114
such as aluminum is formed. The metal plug
114
is also in contact with the gate electrode
109
. The gate electrode
109
and the body region
115
are electrically connected to each other with the metal plug
114
and the impurity diffusion region
111
interposed therebetween.
Further, there may be a structure of the DTMOSFET, as shown in
FIG. 51
, where the metal plug
114
is so formed as to reach the upper surface of the BOX layer
103
and the metal plug
114
and the body region
115
are brought into direct contact with each other, instead of providing the impurity diffusion region
111
in the silicon layer
104
below the metal plug
114
.
Referring to
FIG. 49
, the STI
117
is formed around the source region
156
, the drain region
157
, the body region
115
and the impurity diffusion region
111
with the bold line of the figure as a boundary.
Next, the electrical characteristics of the DTMOSFET will be discussed. In the following discussion, a DTMOSFET using the SOI substrate is referred to as “SOI-DTMOSFET” and an ordinary MOSFET in which the SOI substrate is used and the gate electrode and the body region are not connected to each other is referred to as “SOI-MOSFET”, for distinction. The SOI-DTMOSFET has excellent characteristics when a body voltage is 0.6 V or lower, as compared with the SOI-MOSFET. When the body voltage is 0.6 V or lower, it is possible to prevent a parasitic bipolar transistor using the source region
156
as an emitter, the body region
115
as a base and the drain region
157
as a collector from being driven and further prevent generation of power consumption accompanying the operation of the parasitic bipolar transistor.
Further, in a MOSFET using an ordinary bulk substrate, not the SOI substrate, (hereinafter, referred to as “bulk-MOSFET”), the same effect can be achieved by connecting the silicon substrate and the gate electrode to each other. In the SOI-DTMOSFET, however, respective bottom surfaces of the source region
156
and the drain region
157
can be brought into contact with the upper surface of the BOX layer
103
, as shown in
FIG. 48
, and therefore the area of a pn junction formed of the n
+
-type source region
156
, the n
+
-type drain region
157
and the p-type silicon layer
104
can be reduced. For this reason, in the SOI-DTMOSFET, a pn junction capacitance and a base current can be reduced as compared with the bulk-MOSFET.
Furthermore, since a depletion layer capacitance decreases as the pn junction capacitance decreases, as shown in
FIG. 52
, the SOI-DTMOSFET shows more excellent subthreshold characteristics than the bulk-MOSFET, regardless of whether NMOS or PMOS. Further, in the graph of
FIG. 52
, the horizontal axis indicates a gate voltage V
G
(V) and the vertical axis indicates the drain current I
D
(A), and “S” in the figure represents a subthreshold coefficient.
FIG. 53
is a graph showing a relation between a body bias voltage (the body voltage relative to the source) V
bs
and the threshold voltage V
th
in n-type SOI-MOSFET and SOI-DTMOSFET. Usually, a body voltage which is a reverse bias relative to the source region (in other words, V
bs
<0) is applied to the body region of the SOI-MOSFET. As indicated by the characteristics T
1
, the threshold voltage V
th
increases as the absolute value of the body bias voltage V
bs
increases. The minimum value of the threshold voltage V
th
in the SOI-MOSFET is obtained when the body bias voltage V
bs
is 0 V, being about 0.4 V in the example shown in FIG.
53
.
In contrast to this, in the SOI-DTMOSFET, since the gate electrode and the body region are connected to each other, a body voltage which is a forward bias relative to the source region (in other words, V
bs
>0) is applied to the body region of the SOI-DTMOSFET. In
FIG. 53
, the threshold voltage V
th
of the SOI-DTMOSFET is

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