Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1998-10-30
2002-02-12
Yoo, Do Hyun (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C365S189040, C365S189050, C365S230080
Reexamination Certificate
active
06347357
ABSTRACT:
BACKGROUND OF THE INVENTION
As the computer industry evolves, demands for memory have out-paced the technology of available memory devices. One of these demands is high speed memory compatibility. Thus, in a computer system, such as a personal computer or other computing system, memory subsystems have become an influential component toward the overall performance of the system. Emphasis is now on refining and improving memory devices that provide affordable, zero-wait-state operations.
Generally, volatile memories are either DRAM or static RM (“SRAM”). Each SRAM cell includes plural transistors. Typically the data stored in a SRAM cell is stored by the state of a flip-flop formed by some of the transistors. As long as power is supplied, the flip-flop keeps its data; it does not need refreshing. In a DRAM cell, on the other hand, there typically is one transistor, and data is stored in the form of charge on a capacitor that the transistor accesses. The capacitor dissipates its charge and needs to be refreshed.
These two types of volatile memories have respective advantages and disadvantages. With respect to memory speed, the SRAM is faster than the DRAM due, partially at least, to the nature of the cells. The disadvantage, however, is that because there are more transistors, the SRAM memory is less dense than a DRAM of the same physical size. For instance, static RAMs traditionally have a maximum of one-fourth the number of cells of a DRAM which uses the same technology.
While the DRAM has the advantage of smaller cells and thus higher cell density (and lower cost per bit), one disadvantage is that the DRAM must refresh its memory cells whereas the SRAM does Inot. While the DRAM refreshes and precharges, access to the memory cells is prohibited. This creates an increase in access time, which drawback the static RAUM does not suffer.
However, the speed and functionality of current DREMS are often emphasized less than memory size (storage capacity) and cost. This is evidenced by the fact that DRAM storage capacity density has increased at a rate an order of magnitude greater than its speed. While there has been some improvement in access tire, systems using DRAMs generally have had to achieve their speed elsewhere.
In order to increase system speed, cache memory techniques have recently been applied to DRAM main memory. These approaches have generally been implemented on a circuit board level. That is, a cache memory is frequently a high-speed buffer interposed on the circuit board between the processor chip and the main memory chip. While some efforts have been made by others to integrate a cache with DRAM, we first address the board level approach.
FIG. 1
indicates a prior art configuration (board-level) wherein a processor chip
10
is configured with a cache controller
12
and a cache memory
14
. The main purpose of the cache memory is to maintain frequently accessed data for high speed system access. Cache memory
14
(sometimes called “secondary cache static RAM”) is loaded via a multiplexer
16
from DRAMs
20
,
22
,
24
and
26
. Subsequently, data is accessed at high speeds if stored in cache memory
14
. If not, DRAMs
20
,
22
,
24
and/or
26
load the sought data into cache memory
14
. As seen in
FIG. 1
, cache memory
14
may comprise a SRAM, which is generally faster than DRAMS
20
-
26
.
Various approaches have been proposed for cache memory implementation. These approaches include controlling external cache memory by a controller, such as cache memory
14
and cache controller
12
in
FIG. 1
, or discrete proprietary logic. Notwithstanding its benefits, cache memory techniques complicate another major problem that exists in system design. Memory components and microprocessors are typically manufactured by different companies. This requires the system designer to effectively bridge these elements, using such devices as the cache controller
12
and the multiplexer
16
of FIG.
1
. These bridge components are usually produced by other companies. The different pin configurations and timing requirements of these components makes interfacing them with other devices difficult. Adding a cache memory that is manufactured by yet another company creates further design problems, especially since there is no standard for cache implementation.
Exacerbating the system design problems is the disadvantage that the use of external cache memory (such as cache memory
14
) compromises the main storage access speed. There are mainly two reasons for this compromise. First, and most significant, the main storage access is withheld until a “cache miss” is realized. The penalty associated with this miss can represent up to two wait states for a 50 MHz system. This is in addition to the time required for a main memory access. Second, the prioritized treatment of physical routing and buffers afforded the external cache is usually at the expense of the main memory data and address access path. As illustrated in
FIG. 1
, data from DRAMs
20
,
22
,
24
and
26
can be accessed only through cache memory
14
. The actual delay may be small, but adds up quickly.
A third problem associated with separate cache and main memory is that the time for loading the cache memory from the main memory (“cache fill”) is dependent on the number of inputs to the cache memory from the main memory. Since the number of inputs to the cache memory from the main memory is usually substantially less than the number of bits that the cache memory contains, the cache fill requires many clock cycles. This compromises the speed of the system.
A memory architecture that has been used or suggested for video RAMs (“VRAMs”) is to integrate serial registers with a main memory. VRAMs are specific to video graphics applications. A VRAM may comprise a DRAM with high speed serial registers allowing an additional access port for a line of digital video data. The extra memory used here is known as a SAM (serially addressed memory), which is loaded using transfer cycles. The SAM'S data is output by using a serial clock Hence, access to the registers is serial, not random. Also, there is continuous access to the DRAM so refresh is not an issue as it is in other DRAM applications.
Another implementation that is expected to come to market in 1992 of on-chip cache memory will use a separate cache and cache controller sub-system on the chip. It uses full cache controllers and cache memory implemented in the same way as it would be if external to the chip, i.e. a system approach. This approach is rather complicated and requires a substantial increase in die size. Further, the loading time of the cache memory from the main memory is constrained by the use of input/output cache access ports that are substantially fewer in number than the number of cache memory cells. A cache fill in such a manner takes many clock cycles, whereby system access speed suffers. Such an approach is, in the inventors' views, somewhat cumbersome and less efficient than the present invention.
Still another problem in system design arises when the system has both (a) interleaved memory devices together with (b) external cache memory. Interleaving assigns successive memory locations to physically different memory devices, thereby increasing data access speed. Such interleaving is done for high-speed system access such as burst modes. The added circuitry for cache control and main memory multiplexing usually required by external cache memory creates design problems for effective interleaved memory devices.
Another problem with the prior art arises when memory capacity is to increase. Adding more memory would involve adding more external SRAM cache memory and more cache control logic. For example, doubling the memory size in
FIG. 1
requires not only more DRAM devices required but also another multiplexer and possibly another cache controller. This would obviously add to system power consumption, detract from system reliability, decrease system density, add manufacturing costs and complicate system design.
Another problem concerns the cost of m
Carrigan Donald G.
Jones Oscar Frederick
Mobley Kenneth J.
Sartore Ronald H.
Enhanced Memory Systems Inc.
Hogan & Hartson LLP
Kubida, Esq. William J.
McLean Kimberly
Yoo Do Hyun
LandOfFree
Enhanced DRAM with embedded registers does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Enhanced DRAM with embedded registers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Enhanced DRAM with embedded registers will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2955540