Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2000-08-30
2002-08-20
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S149000, C365S189090
Reexamination Certificate
active
06438020
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to non-volatile semiconductor memory devices and more particularly to a ferroelectric memory device in which a ferroelectric material is used.
2. Description of the Related Art
The capacitance of a capacitor formed of a ferroelectric material (hereinafter referred to as “ferroelectric capacitance”) exhibits hysteresis in the relation between an applied voltage and its polarization. A ferroelectric memory device which utilizes ferroelectric capacitors in its memory cells can retain data which have been written in the ferroelectric capacitors by applying voltages thereto by virtue of their residual polarizations even after the applied voltages become zero. Therefore, a non-volatile ferroelectric memory device can be constructed utilizing such characteristics.
During a reading operation in a ferroelectric memory device, stored data is reproduced by applying a voltage to a ferroelectric capacitor to cause a bit-line voltage, which corresponds to zeros or ones of the data stored in the data cell, to develop and then reading the bit-line differential voltage thus developed in accordance with the polarization direction by a sense amplifier. In order to carry out a correct reading operation with such a structure, it is important to make arrange for the difference between the bit-line differential voltage appearing when “0” is read and that appearing when “1” is read to be sufficiently large.
It is also important for stable reading operations to design the device so that a voltage applied during a writing operation is set to such a value that the polarization of the ferroelectric material is surely reversed.
There has been proposed, for example, in Japanese Unexamined Patent Application, First Publication No. 9-7376, a ferroelectric memory device which is controlled in such a way that a sufficiently large voltage is applied to the ferroelectrics during reading to obtain a sufficient difference between the bit-line differential voltages for reading “0” and “1”, particularly for low-voltage operation of the device. This conventional control method and the structure of the device will now be described with reference to
FIGS. 8
to
10
.
In this conventional control method the pre-charge voltage of the bit lines is set, for the stable reading operation of the device, to a value which is higher than that of the supply voltage for the sense amplifiers and the peripheral circuits of the device.
In the case of a memory device where the pre-charge voltage for the bit lines is not stepped up, the voltage applied to the ferroelectric capacitor during a read operation is determined by the charge-sharing between the ferroelectric capacitance and the parasitic capacitance of the bit lines and is therefore lower than that applied thereto during a write operation. As a result, the read operation will not be stable.
In the ferroelectric memory device disclosed in Japanese Unexamined Patent Application, First Publication No. 9-7376, in order to realize a stable reading operation the pre-charge voltage applied during reading is selected to be higher, so that the voltage applied to the ferroelectric capacitance during reading is equivalent to that applied thereto during writing.
FIG. 8
shows the structure of the above conventional ferroelectric memory. As shown in
FIG. 8
, this memory comprises a step-down power supply circuit
804
provided for reducing the power consumption in a peripheral circuit
802
. That is to say, the supply voltage to the peripheral circuit is a stepped-down supply voltage Vcc as obtained by lowering an external supply voltage Vhp fed from the outside.
On the other hand, bit lines BL
0
and BL
1
are pre-charged with a voltage higher than the stepped-down supply voltage Vcc, for example, with the external supply voltage Vhp fed from the outside. Specifically, a pre-charge circuit
803
is supplied with the external supply voltage Vhp.
FIG. 9
shows the structure of a circuit for the bit-line system of the conventional ferroelectric memory. A memory cell MC
1
is comprised of two ferroelectric capacitors (capacitances) FC
11
and FC
12
and two cell transistors TC
11
and TC
12
. One terminal of the ferroelectric capacitors FC
11
and FC
12
is connected in common to a plate line PL
1
and the other terminal of the ferroelectric capacitors FC
11
and FC
12
is connected to the sources of the cell transistors TC
11
and TC
12
, respectively. The gates of the cell transistors TC
11
and TC
12
are connected in common to a word line WL
1
and the drains of the cell transistors TC
11
and TC
12
are connected to the bit lines BL
0
and BL
1
, respectively. Other memory cells (MC
2
) than the memory cell MC
1
have a circuit structure similar to that of the memory cell MC
1
and their configuration and element sizes are equivalent to those of MC
1
.
With the above circuit structure, the potential of the plate line PL
1
is fixed to a voltage equal to a half of the stepped-down supply voltage Vcc, i.e., Vcc/2.
A sense amplifier (SA)
801
is of the latch type and is constituted by first and second inverters whose input and output terminals are cross-coupled, wherein the first inverter is comprised of a P-channel MOS transistor PM
1
and an N-channel MOS transistor NM
1
connected between the terminals for sense-amplifier activation signals SAP and SAN and the second inverter is comprised of a P-channel MOS transistor PM
2
and an N-channel MOS transistor NM
2
connected between these terminals. The output terminal of the first inverter and the input terminal of the second inverter are connected to the bit line BL
0
, while the input terminal of the first inverter and the output terminal of the second inverter are connected to the bit line BL
1
.
P-channel MOS transistors PM
3
and PM
4
, which are connected respectively between the bit lines BL
0
and BL
1
and a terminal for the supply voltage Vhp and have respective gates supplied with a pre-charge signal PBL, constitute the pre-charge circuit
803
which serves to pre-charge the bit lines when they are turned on.
The output terminals of the sense amplifier (SA)
801
are connected respectively to I/O lines IO
0
and IO
1
through column switches Y
0
and Y
1
whose ON/OFF states are controlled by a column selection signal YSW.
FIG. 10
is a time chart for the description of the operation of the circuits of FIG.
9
and shows each waveform of the signals on the word line WL
1
and the plate line PL
1
, the pre-charge signal PBL, the signals on the bit lines BL
0
and BL
1
and the sense amplifier activation signals SAN and SAP. When the word line WL
1
is brought to a high level during a read operation, voltages determined by the ratios of bit-line parasitic capacitances CB
0
and CB
1
to the capacitances of the ferroelectric capacitors are applied to these ferroelectric capacitors, whereby data is read out.
During a re-writing operation, since the voltage of the plate line PL
1
is at Vcc/2, a voltage equal to Vcc/2 is applied across the terminals of each ferroelectric capacitor.
According to this conventional structure, the voltage applied to the ferroelectric capacitors during reading can be made equivalent to that applied thereto during writing by setting the pre-charge voltage of the bit lines to Vhp which is higher than the voltage Vcc for operating the peripheral circuit
802
. A stable reading operation of the memory can thus be realized.
In the case where a reading operation is carried out with the voltage of the plate line being at Vcc or at the ground potential, since the voltages applied to the ferroelectrics are sufficient, the pre-charge voltage of the bit lines need not be increased and may be at the ground potential or Vcc.
FIG. 5
shows the hysteresis of the ferroelectrics. In
FIG. 5
, the abscissa represents the applied voltage and the ordinate represents the polarization (or charge Q). The hysteresis deteriorates in accordance with the fatigue of and the imprint on the ferroelectric film, which depend on the number of access
Auduong Gene N.
Ho Hoai
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