Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-05-25
2002-12-10
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S341000, C257S339000, C257S409000, C257S496000
Reexamination Certificate
active
06492691
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to MOS technology power devices, such as power MOSFETs, Insulated Gate Bipolar Transistors (IGBTs) and the like. More particularly, the present invention relates to MOS technology power device structures suitable for achieving a high integration density.
2. Discussion of the Related Art
The basic structure of a MOS technology power device is well known. In a lightly doped semiconductor layer of a first conductivity type (“drain layer”), generally formed by epitaxial growth over a heavily doped semiconductor substrate of the same or, as in the case of IGBTs, of a second opposite conductivity type, so-called “body regions” of the second conductivity type are formed. The body regions can be in the form of polygonal cells, for example square, rectangular or hexagonal, or they can be in the form of elongated stripes. The body regions include channel regions which are covered by an insulated gate layer, generally made of polysilicon. Inside the body regions, source regions of the first conductivity type are provided.
Each body region, together with the associated channel regions and source regions, forms an elementary MOS device. All the elementary MOS devices are connected in parallel to each other, and contribute a respective fraction to the overall current of the MOS technology power device.
In the quest to improve the performance of power MOS devices, the density of integration is constantly increasing; in this way, the chip area can be better exploited. An increased density of integration means an increased number of elementary MOS devices integrated in a same chip. This in turn means a progressive reduction of the size of the elementary MOS devices, i.e. of the body regions. A significant improvement in the integration density can be obtained by forming the body regions as elongated stripes instead of square or hexagons.
However, the reduction in size of the body regions poses some problems. Reference is made for example to the case of generally rectangular body regions shown in
FIGS. 1
to
3
.
FIG. 1
is a top plan view of a small portion of a MOS technology power device chip, at the level of the surface of the drain layer
1
which, in the example, is assumed to be of the N conductivity type. The N type drain layer
1
is formed over a substrate
2
which can be of the N conductivity type or of the P conductivity type, depending on the kind of device (FIG.
3
). In
FIG. 1
, four elementary MOS devices are shown. Each elementary MOS device comprises a respective body region
3
, of the P conductivity type. Each body region includes a channel region
4
which, as shown in
FIG. 3
, is covered by an insulated gate
55
including a gate oxide layer
51
and a conductive gate layer
52
, generally made of polysilicon. For the sake of clarity, the source regions are not depicted, since they are not relevant to the following explanation.
The body regions are generally rectangular. As better shown in
FIG. 2
, which is an enlarged view of an end of a body region, due to the reduction in size of the body regions, the short sides of the rectangle are actually rounded. Rh denotes the horizontal radius of the junction between the body region and the drain layer, while Rv in
FIG. 3
denotes the vertical radius of such a junction.
It is generally known that the smaller the radius of a PN junction, the lower the reverse voltage it can sustain before entering breakdown. There is a lower limit in the size of the elementary MOS devices below which the horizontal radius Rh of the junction between the body region and the drain layer becomes more critical than the vertical radius Rv of the same junction, from the viewpoint of junction breakdown. By way of example, it has been verified that with a junction depth of about 2 &mgr;m an early breakdown of the body region-drain layer junction is experienced for body regions smaller than 5 &mgr;m. This poses a serious limitation to the increase of the integration density.
EP-A-0782201 discloses a structure for a MOS technology power device that achieves high integration density without incurring the above mentioned problem. The structure provides for forming the body regions in the form of elongated stripes (“body stripes”), and providing in the drain layer a continuous region of the second conductivity type surrounding all the body stripes, the ends of which are merged with the continuous region. In this way, it is possible to avoid the presence of junctions having a small radius of curvature. The resulting structure is similar to a mesh formed in the drain layer, and is useful for achieving a reduction of the minimum feature size down to 1 to 3 &mgr;m.
However, the provision of the continuous region surrounding the body stripes requires a dedicated mask and a dedicated implant. This makes the above solution rather disadvantageous in the case of MOS technology power devices designed for operating at low voltages (i.e., up to 100 V); these power devices do not need an edge structure (edge ring), so all the process steps necessary for the formation of the continuous doped region surrounding the body stripes are added to the normal manufacturing process flow.
In view of this state of the art, it is an object of the present invention to provide a MOS technology power device structure suitable for achieving a high integration density without exhibiting problems of early junction breakdown, and not requiring additional process steps with respect to the conventional manufacturing process.
SUMMARY OF THE INVENTION
According to the present invention, this and other objects are achieved in a high density MOS technology power device structure, comprising body regions of a first conductivity type formed in a semiconductor layer of a second conductivity type, wherein said body regions comprise at least one plurality of substantially rectilinear and substantially parallel body stripes each joined at its ends to adjacent body stripes by means of junction regions, so that said at least one plurality of body stripes and said junction regions form a continuous, serpentine-shaped body region.
As a result of the present invention, high densities of integration can be achieved. The provision of the body regions in the form of stripes allows increasing the integration density, as mentioned in the above discussion. The width of the stripes can be reduced down to the minimum feature size of the technological process. Additionally, the fact that the stripes are joined at their free, ends by junction regions eliminates the presence of regions having a small horizontal radius of curvature. Thus, early breakdown can be prevented. Compared to the solution proposed in EP-A-0782201, providing for the formation of a continuous region surrounding and merged with the body stripes, the present invention does not need any dedicated process step for its fabrication, and this is a clear advantage.
REFERENCES:
patent: 4015278 (1977-03-01), Fukuta
patent: 4055884 (1977-11-01), Jambotkar
patent: 4072975 (1978-02-01), Ishitani
patent: 4145700 (1979-03-01), Jambotkar
patent: 4206469 (1980-06-01), Hanes et al.
patent: 4261765 (1981-04-01), Komatsu et al.
patent: 4293868 (1981-10-01), Iizuka et al.
patent: 4344081 (1982-08-01), Pao et al.
patent: 4345265 (1982-08-01), Blanchard
patent: 4376286 (1983-03-01), Lidow et al.
patent: 4399449 (1983-08-01), Herman et al.
patent: 4412242 (1983-10-01), Herman et al.
patent: 4414560 (1983-11-01), Lidow
patent: 4416708 (1983-11-01), Abdoulin et al.
patent: 4512816 (1985-04-01), Ramde et al.
patent: 4593302 (1986-06-01), Lidow et al.
patent: 4605948 (1986-08-01), Martinelli
patent: 4642666 (1987-02-01), Lidow et al.
patent: 4680853 (1987-07-01), Lidow et al.
patent: 4705759 (1987-11-01), Lidow et al.
patent: 4716126 (1987-12-01), Cogan
patent: 4754310 (1988-06-01), Coe
patent: 4767722 (1988-08-01), Blanchard
patent: 4798810 (1989-01-01), Blanchard et al.
patent: 4804634 (1989-02-01), Krishna et al.
patent: 4816882 (1989-03-01), Blanchard et al.
patent: 4901127 (1990-0
Frisina Ferruccio
Magri' Angelo
Lee Eddie
Lee Eugene
Morris James H.
Skrivanek, Jr. Robert A.
Wolf Greenfield & Sacks P.C.
LandOfFree
High integration density MOS technology power device structure does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High integration density MOS technology power device structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High integration density MOS technology power device structure will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2952937