Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2000-05-17
2002-02-05
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S758000, C257S750000
Reexamination Certificate
active
06344693
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and to a method for manufacturing a semiconductor device, and more particularly it relates to a method for manufacturing multilayer interconnections.
2. Background of the Invention
The design rule in semiconductor integrated circuits continues to shrink, and with this comes a prominent deterioration of performance caused by delays in interconnections. That is, while the signal delay in interconnections in a semiconductor integrated circuit is determined by the RC constant (R: resistance, C: capacitance) of the interconnection, the increase in the interconnection resistance with a reduction in width of the interconnection, and the increase in capacitance between interconnections caused by a reduced spacing between interconnections create the problem that the above-mentioned RC constant will prevent speed up switching speed of the transistor. At present, an alumina alloy is used as the interconnection material in semiconductor integrated circuits, although copper or silver interconnections are being studied because of their low resistance.
With copper interconnections, because processing is more difficult than with alumina interconnections, a trench is formed in the interlayer insulation film, the interconnection metal being buried therein, the excess metal over the interlayer insulation film being removed using CMP(chemical mechanical polishing). This process is known as a damascene interconnection structure. In this damascene interconnection structure, as shown in
FIG. 16
, if copper is used in the first interconnection layer
6
and second interconnection layer
15
, because copper has a great tendency to oxidize, a first interconnection protective layer
7
and second interconnection protective layer
16
are formed immediately above the copper damascene interconnections, these being made of silicon nitride or silicon oxinitride films. In addition to use these layers as layers that protect the copper interconnections from oxidation, this silicon nitride or silicon oxinitride film are used as the first etching stop film
3
and the second etching stop film
9
as shown in
FIG. 17
, when forming the trench for interconnections.
In order to reduce the capacitance between interconnections, it is effective to use an insulation material that has a lower dielectric constant than the currently used silica (SiO
2
). However, the silicon nitride or silicon oxinitride film used in the damascene interconnection structure has a high dielectric constant of approximately 7, so that even if an insulating material having a low dielectric constant is used to reduce the capacitance between interconnections, that effect is canceled out by the film having a high dielectric constant, so that the overall effect is lessened. Because the interconnection protective film is provided directly above the copper interconnection, and the interconnection trench etching stop film is provided immediately below the interconnection, the interconnection is sandwiched between two high dielectric constant films. For example, in a second example of the past by Igarashi et al (“The Best Combination of Aluminum and Copper Interconnects for High Performance 0.18 &mgr;m CMOS Logic Device”, 1998 International Electron Device Meeting Technical Digest, p. 829), a protective film is disposed immediately above the interconnection, and an etching stop film is disposed immediately below the interconnection (FIG.
17
). In this second past example, after forming a first protective layer
7
on a first interconnection layer
6
, a third insulation film
8
and second etching stop film
9
are formed. Using the second resist (contact hole pattern) as a mask, a second aperture
11
for a contact hole is formed in the second etching stop film
9
. The second resist is removed, and a fourth insulation film
12
is formed, after which a third resist (interconnection trench pattern) is formed. When this is done, an interconnection trench resist pattern that is larger than the contact hole diameter is formed at the top part of the contact hole aperture
11
formed on the second etching stop film
9
. When this resist pattern is used as a mask to perform etching, in the fourth insulation film
12
an interconnection trench that has the third aperture is formed, which has as its bottom the second etching stop film
9
, in a region of the second etching stop film
9
in which there is no contact hole aperture.
In a region of the second etching stop film
9
in which a contact hole aperture
11
is formed, the progressive etching forms a contact hole, which has as its bottom the first protective film
7
. In this condition, the third resist used in etching is removed. Additionally, in order to make contact with the lower-layer first interconnection layer
6
, the first interconnection protective film
7
is etched, thereby completing the contact hole. After that, a copper film is formed over the entire surface, and the CMP method is used to remove the copper over the fourth insulation film
12
, thereby enabling the formation of a inlayed interconnection that is integral with the contact plug.
In the above-noted example of the past, however, there are the following problems.
The first problem is the increase in the capacitance between interconnections. By disposing a silicon nitride film, which has a high dielectric constant, either above, below, or both above and below the interconnection, pairs of interconnections are disposed with a insulation film having a high dielectric constant therebetween, this causes an increase in the capacitance between interconnections, and particularly between horizontal-direction interconnections. If silicon nitride or silicon oxinitride is used in an etching stop film or an interconnection protective film, the high dielectric constant of this substance itself causes an increase in the capacitance between interconnections. In order that there is not an increase in the effective capacitance between interconnections, it is necessary to reduce as much as possible the proportion of a film having a high dielectric constant, or to eliminate it entirely.
The second problem is that, in the case in which the first interconnection is made of copper or the like which does not form an inactive oxide, if plasma CVD is used to form a film containing oxygen, such as an oxide or nitride film as a first interconnection protective film, oxygen ions or oxygen radicals in the plasma gas cause oxidation of the surface of the first interconnection, thereby causing a great increase in the resistance of the interconnection.
The Japanese Unexamined Patent Publication (KOKAI) No. 10-150105 discloses the making of an interlayer insulation film with a inlayed interconnection having a low dielectric constant.
In the above-noted technology, however, because of the low performance as an etching stop film, there is the problem of not being able to achieve the prescribed etching.
Additionally, although there is indication of film growth by the application of a low dielectric constant organic insulation film immediately above the inlayed interconnection, in the general method used for such application, in order to remove water from the surface, a hot plate or the like is used to heat to a temperature of 120° C. immediately before application, and when copper is used as the interconnection material, the heating will be done with the copper in the exposed condition, so that the copper surface is easily oxidized.
Accordingly, it is an object of the present invention to improve on the above-noted problems with the prior art, by providing a semiconductor device and method for manufacturing a semiconductor device, which in particular makes use of a low dielectric constant film as a protective film immediately above an inlayed copper interconnection, and a low dielectric constant insulation film is used as an etching stop film immediately below the inlayed interconnection. In the present invention, by forming an organic insulation film
Hayashi Yoshihiro
Kawahara Jun
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