Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2001-08-01
2002-12-03
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S228000, C365S189050
Reexamination Certificate
active
06490216
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90117784, filed Jul. 20, 2001.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a memory refresh circuit and a memory refresh method. More particularly, the present invention relates to a memory refresh method or circuit capable of refreshing memory cells along a word line containing stored data.
2. Description of Related Art
In general, a dynamic random access memory (DRAM) unit consists of a transistor and a capacitor. By transferring electric charges to the capacitor or discharging electric charges from the capacitor, different storage states such as ‘1’ and ‘0’ are produced. However, some of the charges residing inside the capacitor may leak out over time, leading to a drop in voltage. When sufficient electric charges leak away, different storage states in a memory cell are hard to distinguish. To maintain a particular storage stage, refresh cycles are conducted from time to time so that charges inside the capacitor are replenished. Although refresh cycles can restore a minimal voltage level, refreshing entails current loss and consequently an increase in power consumption.
At present, memory refreshing is conducted on memory cells along all word lines no matter whether a particular word line holds data or not. In other words, word lines that do not hold anything are still refreshed. Ultimately, a longer refreshing cycle than necessary is carried out and more power than necessary is wasted in the refresh operation.
Following the rapid development of portable electronic equipment and the rapid increase in memory capacity, over-consumption of electric power is an important issue. Too much energy wasted in refreshing shortens workable time. Hence, any circuits or methods that can reduce the number of refresh cycles are highly beneficial.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a selective memory refresh circuit and method that refresh memory cells along a word line containing stored data but skip those memory cells along a word line containing no data.
A second object of the invention is to provide a selective memory refresh circuit and method that reduce power consumption and shorten refreshing time in each refresh cycle.
A third object of the invention is to provide a selective memory refresh circuit and method that utilize a release signal to release unused word line addresses so that the unused word lines are skipped during refreshing.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a selective memory refresh circuit for refreshing a memory cell array. The memory cell array comprises of a plurality of rows and columns. The memory cell array also includes a plurality of word lines with each column corresponding to a word line. The selective memory refresh circuit includes a plurality of word line refresh selection circuits coupled to various word lines for determining if the particular word line needs to be refresh during a refresh cycle. The word line refresh selection circuit further includes a word line address latching device and word line refresh comparison circuit. The word line address latching device receives a word line pre-decode signal, a release signal and a triggering signal and outputs a word line latching signal. The word line refresh comparison circuit receives the word line pre-decode signal and the word line latching signal and transmitting the result of comparison to a word line driver. When the triggering signal activates the word line, the word line latching signal becomes a first level signal (for example, a high potential level) to indicate the presence of stored data in the memory cells connected to the word line. On issuing a release signal, the word line latching signal switches to a second level signal (for example, a low potential level) to indicate the absence of stored data in the memory cells connected to the word line. During a refreshing cycle, if the word line latching signal is a first level signal, memory cells along the word line are refreshed. On the contrary, if the word line latching signal is a second level signal, memory refresh of the word line is no longer conducted.
This invention also provides a method for conducting a selective memory refresh. The method is applied to refresh a memory array having a plurality of rows and columns as well as a plurality of word lines, wherein each column corresponds to a word line. First, a refresh cycle is initiated. The plurality of memory cells along a word line is checked to determine if the memory cells contain any stored data. If the word line contains stored data, memory cells along the word line are refreshed. Conversely, if the word line contains no stored data, memory cells along the word line are skipped without conducting a refresh operation. The checking and refreshing steps are repeated until all word lines are processed. When all the word lines are appropriately processed, a refresh cycle is completed.
In brief, if the word line contains stored data, the word line is refreshed. On the contrary, if the word line contains no stored data, refreshing of the word line is not conducted. Applying this scheme to refresh the memory array, refreshing time is shortened and overall power consumption for the refreshing operation is reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 6094705 (2000-07-01), Song
patent: 6178479 (2001-01-01), Vishin
patent: 6392952 (2002-05-01), Chen et al.
patent: 6404690 (2002-06-01), Johnson et al.
Chen Juei-Lung
Huang Shih-Huang
Nguyen Tan T.
United Microelectronics Corp.
Wu Charles C. H.
Wu & Cheung, LLP
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