Error recovery mechanism for a high-performance interconnect

Details Error recovery mechanism for a high-performance interconnect Error recovery mechanism for a high-performance interconnect

1999-11-09

2002-11-26

Baderman, Scott (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S043000

Reexamination Certificate

active

06487679

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a data processing system in general, and in particular to a parity error recovery mechanism within a data processing system. Still more particularly, the present invention relates to a parity error recovery mechanism for an interconnect within a data processing system.
2. Description of the Prior Art
Within a data processing system, various devices, such as a processor, a system memory, etc., are typically interconnected with each other via a group of wires known as a bus. In fact, the technique of using a bus to transmit data has been in common use since the early days of electronic computers. Two types of buses are typically utilized in a data processing system, namely, a data bus and an address bus. As their names imply, the data bus is utilized to transmit data, and the address bus is utilized to transmit addresses. There are many advantages in using a single interconnect such as a bus for interconnecting devices within a data processing system. For example, new devices can easily be added or even be ported between data processing systems that use a common bus.
Occasionally, a parity error may occur on a bus within a data processing system. According to the prior art, bus parity error recovery is typically handled by a group of pins known as error correction code (ECC) pins that are built into certain devices. However, additional area is required on a device to accommodate such ECC pins, not to mention that the latency of data transfer on the bus will be increased due to the additional time required to generate ECC at a bus master and to check the ECC (and possibly correct corrupted data/address bits) at a bus slave. Thus, it would be desirable to provide an improved parity error recovery mechanism for a bus within a data processing system such that ECC pins are not required.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the present invention, a data processing system includes a bus connected between a bus master and a bus slave. In response to a parity error occurring on the bus, the bus slave issues a bus parity error response to the bus master via the bus. After waiting for a predetermined number of bus cycles to allow the bus to idle, the bus master then issues a RESTART bus command packet to the bus slave via the bus to clear the parity error. If the RESTART bus command packet is received correctly, the slave bus will remove the bus parity error response such that normal bus communication may resume.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.


REFERENCES:
patent: 5774679 (1998-06-01), Kondo et al.
patent: 6049894 (2000-04-01), Gates

Affiliated with

Also associated with

Rating

Error recovery mechanism for a high-performance interconnect does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Error recovery mechanism for a high-performance interconnect, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Error recovery mechanism for a high-performance interconnect will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2947450