Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-09-05
2002-11-05
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S384000, C257S401000
Reexamination Certificate
active
06476449
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to improved silicide blocks for semiconductor devices, and in particular, to silicide-blocking processes, masks, and silicide-blocked device structures, that improve electro-static discharge (ESD) protection in semiconductor integrated circuit (IC) devices.
2. Background Art
The silicide block has been widely used to create a portion of non-silicided surface in an otherwise silicided diffusion region of a MOS transistor. The silicide block is known to improve, to a certain extent, the ESD performance of a silicide (or salicide) NMOS. The non-silicide region typically represents a high sheet resistance region, and the silicide region represents a low sheet resistance region. The silicide and non-silicide regions are typically formed by photo processing through a patterned silicide/salicide block mask, followed by photo etching and certain metal etching and annealing processes.
FIGS. 1 and 2
illustrate a conventional NMOS transistor
20
having a silicided source/drain (S/D) diffusion
22
, and strips of non-silicided diffusion
24
that are processed by a silicide block mask. In particular, there is a polysilicon gate
26
, a first diffusion (e.g., source) region
28
and a second diffusion (e.g., drain) region
30
, with a first metal bus
32
extending in the drain region
30
and a second metal bus
34
extending in the source region
28
. An anode
36
is coupled to the first metal bus
32
and a cathode
38
is coupled to the second metal bus
34
. A channel
40
is defined between the diffusion regions
28
and
30
.
FIG. 3
illustrates a conventional silicide-block mask
50
in clear field, and
FIG. 4
illustrates a conventional silicide-block mask
52
in dark field. The mask
50
in
FIG. 3
is suitable for metal (e.g., titanium) etching with a first type of (e.g., positive or negative) photoresist, while the mask
52
in
FIG. 4
is suitable for metal (e.g., titanium) etching with a second type of (e.g., negative or positive) photoresist. Each mask
50
and
52
has respective salicide block mask windows
54
and
56
that is positioned relative to the active region
42
of the transistor
20
at the locations where the strips of non-silicided diffusion
24
are to be located. The terms “clear field” and “dark field” refer to the degree of transparency of the field or background of the photo mask
50
or
52
. For example, for a contact mask, the photo patterns can be a number of tiny shaped elements which define where the contacts will be located upon alignment with the wafer by a photo (e.g., exposure or etching) process. If the contact (photo) mask is clear field, the mask is almost entirely transparent except that the contact patterns (i.e., the shaped elements) will be black. Conversely, if the contact (photo) mask is dark field, the mask appears to be almost entirely black or dark, except that the contact patterns (i.e., the shaped elements) will be transparent and will resemble windows or openings.
In a typical salicide process, both the polysilicon and n+ diffusions have silicided surfaces for high-speed applications. The silicide block can also be used to create a non-silicided surface for polysilicon resistors, so that it is easier to obtain a reasonable-sized polysilicon resistor with desirable resistance. Here, it is known that a salicide (self-aligned silicidation) process typically means that both the diffusion region and the polysilicon gate have silicided surfaces.
Unfortunately, silicide blocks suffer from some drawbacks. For example, the drain resistance is significantly increased (e.g., the silicide-blocked n+ sheet resistance is 30 to 40 ohms per square, versus 2 to 3 ohms per square for silicided diffusion), and the speed of the NMOS transistor is degraded. In addition, the increased drain resistance of an input pad ESD protection device may cause the input-pad transient voltage to build up during an ESD event, so that the internal circuit element may get damaged.
Therefore, there remains a need for an improved silicide block that overcomes the drawbacks set forth above.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide silicided and non-silicided regions in semiconductor processing while overcoming the problems identified above.
It is another object of the present invention to minimize the increase in the drain resistance in silicide or salicide block processing.
It is yet another object of the present invention to provide semiconductor devices that utilize silicide or salicide block processing and which are useful for high-speed (e.g., input, output, I/O) applications.
It is yet another object of the present invention to provide semiconductor devices that utilize silicide or salicide block processing and which provide effective ESD protection.
It is yet another object of the present invention to provide suicide or salicide block processing that is simple to implement.
It is yet another object of the present invention to provide silicide or salicide block processing that only requires one mask change to improve ESD protection and I/O speed.
To accomplish the objectives of the present invention, there is provided a semiconductor device that has a first diffusion region having a silicided portion and a non-silicided portion. The device also has a second diffusion region, and a channel region between the first and second diffusion regions. The non-silicided portion of the first diffusion region has a plurality of non-silicided regions.
According to various embodiments of the present invention, the plurality of non-silicided regions can define at least one silicided path between adjacent non-silicided regions. At least some of the silicided paths can be parallel to each other. The plurality of non-silicided regions can be arranged in separate rows, or they can be arranged in an arbitrary manner. The plurality of non-silicided regions can have different sizes, shapes, and orientations.
According to yet another embodiment of the present invention, the second diffusion region also has a silicided portion and a non-silicided portion, with the non-silicided portion of the second diffusion region having a plurality of non-silicided regions.
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US 6,351,012, 2/2002, Hirata (withdrawn)
Ngo Ngan V.
Sun Raymond
Winbond Electronics Corp.
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