Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-06-30
2002-12-24
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S639000, C257S405000, C257S410000
Reexamination Certificate
active
06498374
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a MOS semiconductor device in which a post oxide film is formed on a surface of a gate electrode and a semiconductor substrate.
BACKGROUND OF THE INVENTION
As a method to prevent deterioration in a withstand voltage of a gate insulating film of a silicon MOS FET, there has been heretofore a technology called post oxidation. A post oxide film means an oxide film formed on a surface of a gate electrode and a semiconductor substrate in order to protect a gate insulating film in a corner portion of the gate electrode. An outline of a MOS semiconductor device in which a post oxide film is formed is shown in
FIG. 1-A
. A post oxide film
128
is formed on a gate electrode
127
, an n-type diffusion layer
135
, and a p-type diffusion layer
136
.
FIG. 1-B
is a section view showing a structure after performing a post oxidation in the manufacturing steps of the MOS semiconductor device, which shows a corner portion of the gate electrode
127
. As shown in
FIG. 18
, the gate insulating film
125
is formed on a silicon substrate
110
, and a gate electrode (polysilicon gate electrode)
127
formed of polysilicon is selectively formed on the gate insulating film
125
. Thereafter, a post oxidation is conducted, and then a gate post oxide film
128
is formed on the gate electrode
127
and the semiconductor substrate
110
.
In the post oxidation steps for forming such a gate oxide film, also the gate electrode
127
is oxidized together with the silicon substrate
110
, and hence a thickness of an oxide film in a corner portion of the gate electrode
127
is increased. Accordingly, the radius of curvature of the corner portion of the gate electrode
127
becomes large, and an electric field concentration at a corner portion of a gate electrode of a MOS transistor can be avoided.
Furthermore, it is possible to prevent a deterioration of a gate insulating film at the corner portion of the gate electrode in manufacturing steps of the MOS transistor.
However, in the step for forming the gate post oxide film
128
, the silicon substrate
110
is also oxidized together with polysilicon forming the gate electrode
127
, and an oxide film
125
having a larger thickness than required is formed in the corner portion of the gate electrode
127
. Thus, because an apparent thickness of the gate electrode oxide film
125
is large, a voltage applied to the gate oxide film
125
is weakened, and a gate voltage is lowered, resulting in deterioration of controllability of the MOS transistor. When the MOS transistor is operated in this state, an absolute value of the threshold voltage at the microfabricated channel region is substantially lowered. For this reason, an off leak current flowing in turning off the MOS transistor may increase.
To form an extension diffusion layer
132
of a source/drain electrode, the post oxide film
128
is used as a protection oxide film in ion implantation. In this case, impurity ions are taken into the post oxide film
128
, and hence a dose of impurities implanted into the silicon substrate
110
is reduced. Moreover, for the foregoing reason, ion implantation must be performed in consideration of a thickness of the gate -post oxide film, and the implanted ions create a wide impurity distribution. Accordingly, it is impossible to form a precise impurity concentration profile.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a semiconductor device and a manufacturing method for the same, which are capable of suppressing occurrence of a leak current at a corner portion of a gate electrode, and suppressing a reduction in a dose of impurities implanted into a substrate in ion implantation in forming a source/drain diffusion layer.
A semiconductor device of the present invention has the following constitution to achieve the foregoing and other objects.
The semiconductor device of the present invention comprises a semiconductor substrate; a gate insulating film formed on the semiconductor substrate, the gate insulating film containing nitrogen; a gate electrode selectively formed on said gate insulating film; and an oxide film formed on a surface of the gate electrode and the semiconductor substrate, wherein a thickness of a portion of the gate insulating film closer to the semiconductor substrate is one third or less of that of the gate insulating film closer to a corner portion of the gate electrode.
The gate insulating film is allowed to contain nitrogen, so that an increase in a thickness of the gate insulating film at the corner portion of the gate electrode can be controlled. Thus, it is possible to prevent lowering of a gate voltage.
Furthermore, in the semiconductor device of the present invention, the gate insulating film formed under the gate electrode is an oxide film containing nitrogen at a concentration ranging from about 2% to 10%.
By setting the nitrogen concentration at the foregoing range, a dielectric constant of the gate insulating film is lowered, and hence a reduction in a source-drain current can be prevented.
Still furthermore, in the semiconductor device of the present invention, the gate insulating film has a nitrogen concentration, a peak of which is positioned in the vicinity of the surface of the semiconductor substrate.
Since the peak position of the nitrogen concentration is located in the surface of the semiconductor substrate, oxidation dose not proceed toward the semiconductor substrate, while allowing oxidation dose proceed toward the side surface of the gate electrode.
A manufacturing method of the present invention comprises the steps of: forming a gate insulating film on a semiconductor substrate, the gate insulating film containing nitrogen; forming a gate electrode selectively on the gate insulating film; and
performing a post oxidation after forming the gate electrode to form an oxide film on a surface of the gate electrode and the semiconductor substrate.
By permitting the gate insulating film to contain nitrogen, it is possible to suppress an increase in the thickness of the gate insulating film beyond that required, and it is also possible to prevent lowering of the gate voltage while, improving the controllability of the MOS transistor.
Furthermore, in the manufacturing method of the present invention, a thickness of a portion of the gate insulating film closer to the semiconductor substrate is one third or less of a thickness of a portion of the gate insulating film closer to a corner portion of the gate electrode.
Still furthermore, in the manufacturing method of the present invention, the gate insulating film just under the gate electrode is an oxide film containing nitrogen at a concentration ranging from about 2% to 10%.
Still furthermore, in the manufacturing method of the present invention, the gate insulating film has a nitrogen concentration, a peak of which is located in the vicinity of the surface of the semiconductor substrate.
Since a peak position of a nitrogen concentration is located in the surface of the semiconductor substrate, oxidation which is about to proceed toward the semiconductor substrate can be stopped, while allowing oxidation to proceed toward the side surface of the gate electrode.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
REFERENCES:
patent: 6069041 (2000-05-01), Tanigami et al.
patent: 07030113 (1995-01-01), None
patent: 9-312393 (1997-12-01), None
patent: 10-163348 (1998-06-01), None
Dickey Thomas
Foley & Lardner
Kabushiki Kaisha Toshiba
Tran Minh Loan
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