Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-10-12
2002-02-26
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S637000, C438S638000, C438S666000, C438S687000
Reexamination Certificate
active
06350675
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically, in the formation of self-aligned dual damascene interconnects and vias, which incorporates low dielectric constant intermetal dielectrics (IMD) and utilizes silylated top surface imaging (TSI) photoresist, with a single or multi-step selective reactive ion etch (RIE) process, to form trench/via opening.
(2) Description of the Related Art
As a background to the current invention, the damascene processing is an alternative method for fabricating planar interconnects. Damascene wiring interconnects (and/or studs) are formed by depositing a dielectric layer on a planar surface, patterning it using photolithography and oxide reactive ion etch (RIE), then filling the recesses with conductive metal. The excess metal is removed by chemical mechanical polishing (CMP), while the troughs or channels remain filled with metal. For example, damascene wiring lines can be used to form bit lines in DRAM devices, with processing similar to the formation of W studs in the logic and DRAM devices.
Key to the damascene processing approach is that the deposited conductive metal is deposited into a previously deposited patterned insulator. This is desirable because mask alignment, dimensional control, rework, and the etching process are all easier when applied to a dielectric rather than metal films. Damascene processing achieves these benefits by shifting the enhanced filling and planarization requirements from dielectric to metal films, and by shifting control over interconnect thickness from metal deposition to insulator patterning and metal CMP.
It remains a challenge in dual damascene processing to avoid damage to low dielectric constant insulators, i.e., organically based or carbon doped silicon dioxide materials. One significant problem is the degradation of the low dielectric constant materials during photoresist stripping with oxygen plasma ashing, wherein oxygen free radials react with carbon and hydrogen contained in low dielectric materials. Especially when patterning a via opening in the first level of a dual damascene, utilizing conventional photoresist processes, other deleterious effects can also occur to the low dielectric constant materials, e.g., bowing, profile distortion, increase in dielectric constant, and via poisoning are just some degradation effects. In addition, etching of via etch stop layers, i.e., silicon nitride, can cause gouging of the low dielectric constant organic material just below the stop layer. Post-etch solvent cleaning after the low dielectric material etch, can also attack the nitride stop layer/low dielectric constant material interface.
The related Prior Art background patents will now be described in this section.
U.S. Pat. No. 5,935,762 entitled “Two-Layered TSI Process for Dual Damascene Patterning” granted Aug. 10, 1999 to Dai et al. describes a method for forming dual damascene patterns using a silylation process. A substrate is provided with a tri-layer of insulation formed thereon. A first layer of silylation photoresist is formed on the substrate and is imaged with a hole pattern by exposure through a mask. The hole pattern is then etched in the first photoresist. A second layer of photoresist is formed, and is imaged with a line pattern aligned with the previous hole pattern by exposure through a mask. The line pattern in the second photoresist is etched. The hole pattern in the first photoresist is transferred into the top layer of composite insulation first and then into the middle etch-stop layer by successive etching. Through a series of process steps, hole and line patterns are formed in the insulation layer, and metal is deposited in a dual damascene process.
U.S. Pat. No. 5,877,075 entitled “Dual Damascene Process Using Single Photoresist Process” granted Mar. 2, 1999 to Dai et al. describes a dual damascene process using a silylation process with a single photoresist process. A substrate is provided with a tri-layer of insulation formed thereon. A layer of photoresist is formed on the substrate and is imaged with a hole pattern by exposure through a dark field mask. Hole is formed in the photoresist by a wet etch. As a key step, the photoresist is next subjected to post-exposure bake such that the sensitivity of the photoresist is still retained. The same photoresist layer is then exposed for the second time for aligned line patterning using a “clear-field” mask. The line patterned region is cross-linked by performing pre-silylation bake, which region in turn is not affected by the subsequent silylation process that forms a silicon rich mask in the field surrounding the hole and line patterns. Through a series of process steps, hole and line patterns are formed in the insulation layer, and metal is deposited in a dual damascene process.
U.S. Pat. No. 5,741,626 entitled “Method for Forming a Dielectric Tantalum Nitride Layer as an Antireflective Coating (ARC)” granted Apr. 21, 1998 to Jain et al. describes a process with an anti-reflective Ta
3
N
5
coating which can be used in a dual damascene structure and for I line or G line lithographies. In addition, the Ta
3
N
5
coating may also be used as an etch stop and a barrier layer. A dual damascene structure is formed by depositing a first dielectric layer. A dielectric tantalum nitride layer is deposited on top of the first dielectric layer. A second dielectric layer is deposited on the tantalum nitride layer. A dual damascene opening is etched into the dielectric layers by patterning a first opening portion and a second opening portion using photolithography operations.
U.S. Pat. No. 5,906,911 entitled “Process of Forming a Dual Damascene Structure in a Single Photoresist Film” granted May 25, 1999 to Cote describes a dual damascene process using just one single layer of photoresist with two photomasks and selective silylation. The process includes the steps of forming a photoresist film on a substrate, pattern exposing the photoresist film to form a first pattern in the photoresist film, and forming an etch resistant layer in the first pattern. The photoresist film is pattern exposed a second time to form a second pattern in the photoresist film. After several more process steps and etching, dual damascene trench and via opens are formed.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide an improved method of forming semiconductor integrated circuit devices, and more specifically, in the formation of self-aligned dual damascene interconnects and vias, which incorporates low dielectric constant intermetal dielectrics (IMD) and utilizes silylated top surface imaging (TSI) photoresist, with a single or multi-step selective reactive ion etch (RIE) process, to form trench/via opening. The unexposed resist regions are removed by selective etching of this non-silylated material using either an oxygen plasma, or SO
2
or SO
3
, plasmas or gases.
The low dielectric constant materials, utilized in this invention, consist of either an organic based material or a carbon doped silicon dioxide, and various combinations of the organic based material and carbon doped silicon dioxide. The organic based materials consists of, but are not restricted to, polyimide, “FLARE” (source Allied Signal, now Honeywell), “SILK” (source Dow Chemical).
In the first embodiment of this invention, provided are the following: a semiconductor silicon substrate with an interlayer dielectric (ILD) layer thereon, with a level of metal wiring being defined and embedded in a layer of insulator. The first embodiment of the present invention starts with these conventional layers being provided. A bottom passivation layer is deposited on the metal wiring layer. Next, a low dielectric constant material layer is deposited on the bottom passivational layer. The low dielectric constant material consists of either an organic based material or a carbon doped silicon dioxide. In the first embodiment of this invention, a thin di
Chooi Simon
Gupta Subhash
Xu Yi
Zhou Mei-Sheng
Chartered Semiconductor Manufacturing Ltd.
Gurley Lynne
Niebling John F.
Pike Rosemary L. S.
Saile George O.
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